Lines Matching +full:stm32 +full:- +full:rcc
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "st,stm32-timers";
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
84 clock-names = "int";
88 compatible = "st,stm32-pwm";
89 #pwm-cells = <3>;
94 compatible = "st,stm32-timer-trigger";
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "st,stm32-timers";
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
106 clock-names = "int";
110 compatible = "st,stm32-pwm";
111 #pwm-cells = <3>;
116 compatible = "st,stm32-timer-trigger";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "st,stm32-timers";
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
128 clock-names = "int";
132 compatible = "st,stm32-pwm";
133 #pwm-cells = <3>;
138 compatible = "st,stm32-timer-trigger";
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "st,stm32-timers";
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
150 clock-names = "int";
154 compatible = "st,stm32-pwm";
155 #pwm-cells = <3>;
160 compatible = "st,stm32-timer-trigger";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "st,stm32-timers";
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
172 clock-names = "int";
176 compatible = "st,stm32-timer-trigger";
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "st,stm32-timers";
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
188 clock-names = "int";
192 compatible = "st,stm32-timer-trigger";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "st,stm32-timers";
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
204 clock-names = "int";
208 compatible = "st,stm32-pwm";
209 #pwm-cells = <3>;
214 compatible = "st,stm32-timer-trigger";
221 compatible = "st,stm32-timers";
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
224 clock-names = "int";
228 compatible = "st,stm32-pwm";
229 #pwm-cells = <3>;
235 compatible = "st,stm32-timers";
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
238 clock-names = "int";
242 compatible = "st,stm32-pwm";
243 #pwm-cells = <3>;
249 compatible = "st,stm32-rtc";
251 clocks = <&rcc 1 CLK_RTC>;
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
254 interrupt-parent = <&exti>;
261 #address-cells = <1>;
262 #size-cells = <0>;
263 compatible = "st,stm32f7-spi";
266 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>;
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "st,stm32f7-spi";
276 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>;
281 compatible = "st,stm32f7-uart";
284 clocks = <&rcc 1 CLK_USART2>;
289 compatible = "st,stm32f7-uart";
292 clocks = <&rcc 1 CLK_USART3>;
297 compatible = "st,stm32f7-uart";
300 clocks = <&rcc 1 CLK_UART4>;
305 compatible = "st,stm32f7-uart";
308 clocks = <&rcc 1 CLK_UART5>;
313 compatible = "st,stm32f7-i2c";
317 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
318 clocks = <&rcc 1 CLK_I2C1>;
319 #address-cells = <1>;
320 #size-cells = <0>;
325 compatible = "st,stm32f7-i2c";
329 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
330 clocks = <&rcc 1 CLK_I2C2>;
331 #address-cells = <1>;
332 #size-cells = <0>;
337 compatible = "st,stm32f7-i2c";
341 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
342 clocks = <&rcc 1 CLK_I2C3>;
343 #address-cells = <1>;
344 #size-cells = <0>;
349 compatible = "st,stm32f7-i2c";
353 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
354 clocks = <&rcc 1 CLK_I2C4>;
355 #address-cells = <1>;
356 #size-cells = <0>;
361 compatible = "st,stm32f4-bxcan";
364 interrupt-names = "tx", "rx0", "rx1", "sce";
365 resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
366 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
367 st,can-primary;
373 compatible = "st,stm32f4-gcan", "syscon";
375 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
379 compatible = "st,stm32f4-bxcan";
382 interrupt-names = "tx", "rx0", "rx1", "sce";
383 resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
384 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
385 st,can-secondary;
391 compatible = "st,stm32-cec";
394 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
395 clock-names = "cec", "hdmi-cec";
400 compatible = "st,stm32f7-uart";
403 clocks = <&rcc 1 CLK_UART7>;
408 compatible = "st,stm32f7-uart";
411 clocks = <&rcc 1 CLK_UART8>;
416 #address-cells = <1>;
417 #size-cells = <0>;
418 compatible = "st,stm32-timers";
420 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
421 clock-names = "int";
425 compatible = "st,stm32-pwm";
426 #pwm-cells = <3>;
431 compatible = "st,stm32-timer-trigger";
438 #address-cells = <1>;
439 #size-cells = <0>;
440 compatible = "st,stm32-timers";
442 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
443 clock-names = "int";
447 compatible = "st,stm32-pwm";
448 #pwm-cells = <3>;
453 compatible = "st,stm32-timer-trigger";
460 compatible = "st,stm32f7-uart";
463 clocks = <&rcc 1 CLK_USART1>;
468 compatible = "st,stm32f7-uart";
471 clocks = <&rcc 1 CLK_USART6>;
477 arm,primecell-periphid = <0x00880180>;
479 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
480 clock-names = "apb_pclk";
482 max-frequency = <48000000>;
488 arm,primecell-periphid = <0x00880180>;
490 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
491 clock-names = "apb_pclk";
493 max-frequency = <48000000>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "st,stm32f7-spi";
503 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "st,stm32f7-spi";
513 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>;
518 compatible = "st,stm32-syscfg", "syscon";
520 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>;
523 exti: interrupt-controller@40013c00 {
524 compatible = "st,stm32-exti";
525 interrupt-controller;
526 #interrupt-cells = <2>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "st,stm32-timers";
536 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
537 clock-names = "int";
541 compatible = "st,stm32-pwm";
542 #pwm-cells = <3>;
547 compatible = "st,stm32-timer-trigger";
554 compatible = "st,stm32-timers";
556 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
557 clock-names = "int";
561 compatible = "st,stm32-pwm";
562 #pwm-cells = <3>;
568 compatible = "st,stm32-timers";
570 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
571 clock-names = "int";
575 compatible = "st,stm32-pwm";
576 #pwm-cells = <3>;
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "st,stm32f7-spi";
587 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>;
592 #address-cells = <1>;
593 #size-cells = <0>;
594 compatible = "st,stm32f7-spi";
597 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>;
601 ltdc: display-controller@40016800 {
602 compatible = "st,stm32-ltdc";
605 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
606 clocks = <&rcc 1 CLK_LCD>;
607 clock-names = "lcd";
611 pwrcfg: power-config@40007000 {
612 compatible = "st,stm32-power-config", "syscon";
617 compatible = "st,stm32f7-crc";
619 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
623 rcc: rcc@40023800 { label
624 #reset-cells = <1>;
625 #clock-cells = <2>;
626 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
630 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
631 assigned-clock-rates = <1000000>;
634 dma1: dma-controller@40026000 {
635 compatible = "st,stm32-dma";
645 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
646 #dma-cells = <4>;
650 dma2: dma-controller@40026400 {
651 compatible = "st,stm32-dma";
661 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
662 #dma-cells = <4>;
668 compatible = "st,stm32f7-hsotg";
671 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
672 clock-names = "otg";
673 g-rx-fifo-size = <256>;
674 g-np-tx-fifo-size = <32>;
675 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
680 compatible = "st,stm32f4x9-fsotg";
683 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
684 clock-names = "otg";
691 clocks = <&rcc 1 0>;