dts/renesas/sh73a0.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 	interrupt-parent = <&gic>;
15 	#address-cells = <1>;
16 	#size-cells = <1>;
19 		#address-cells = <1>;
20 		#size-cells = <0>;
24 			compatible = "arm,cortex-a9";
26 			clock-frequency = <1196000000>;
27 			clocks = <&cpg_clocks SH73A0_CLK_Z>;
28 			power-domains = <&pd_a2sl>;
29 			next-level-cache = <&L2>;
33 			compatible = "arm,cortex-a9";
35 			clock-frequency = <1196000000>;
36 			clocks = <&cpg_clocks SH73A0_CLK_Z>;
37 			power-domains = <&pd_a2sl>;
38 			next-level-cache = <&L2>;
43 		compatible = "arm,cortex-a9-global-timer";
46 		clocks = <&periph_clk>;
50 		compatible = "arm,cortex-a9-twd-timer";
53 		clocks = <&periph_clk>;
56 	gic: interrupt-controller@f0001000 {
57 		compatible = "arm,cortex-a9-gic";
58 		#interrupt-cells = <3>;
59 		interrupt-controller;
64 	L2: cache-controller@f0100000 {
65 		compatible = "arm,pl310-cache";
68 		power-domains = <&pd_a3sm>;
69 		arm,data-latency = <3 3 3>;
70 		arm,tag-latency = <2 2 2>;
71 		arm,shared-override;
72 		cache-unified;
73 		cache-level = <2>;
76 	sbsc2: memory-controller@fb400000 {
77 		compatible = "renesas,sbsc-sh73a0";
81 		interrupt-names = "sec", "temp";
82 		power-domains = <&pd_a4bc1>;
85 	sbsc1: memory-controller@fe400000 {
86 		compatible = "renesas,sbsc-sh73a0";
90 		interrupt-names = "sec", "temp";
91 		power-domains = <&pd_a4bc0>;
95 		compatible = "arm,cortex-a9-pmu";
98 		interrupt-affinity = <&cpu0>, <&cpu1>;
102 		compatible = "renesas,sh73a0-cmt1";
105 		clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
106 		clock-names = "fck";
107 		power-domains = <&pd_c5>;
111 	irqpin0: interrupt-controller@e6900000 {
112 		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
113 		#interrupt-cells = <2>;
114 		interrupt-controller;
128 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
129 		power-domains = <&pd_a4s>;
130 		control-parent;
133 	irqpin1: interrupt-controller@e6900004 {
134 		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
135 		#interrupt-cells = <2>;
136 		interrupt-controller;
150 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
151 		power-domains = <&pd_a4s>;
152 		control-parent;
155 	irqpin2: interrupt-controller@e6900008 {
156 		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
157 		#interrupt-cells = <2>;
158 		interrupt-controller;
172 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
173 		power-domains = <&pd_a4s>;
174 		control-parent;
177 	irqpin3: interrupt-controller@e690000c {
178 		compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
179 		#interrupt-cells = <2>;
180 		interrupt-controller;
194 		clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
195 		power-domains = <&pd_a4s>;
196 		control-parent;
200 		#address-cells = <1>;
201 		#size-cells = <0>;
202 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
208 		clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
209 		power-domains = <&pd_a3sp>;
214 		#address-cells = <1>;
215 		#size-cells = <0>;
216 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
222 		clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
223 		power-domains = <&pd_a3sp>;
228 		#address-cells = <1>;
229 		#size-cells = <0>;
230 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
236 		clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
237 		power-domains = <&pd_a3sp>;
242 		#address-cells = <1>;
243 		#size-cells = <0>;
244 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
250 		clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
251 		power-domains = <&pd_a3sp>;
256 		#address-cells = <1>;
257 		#size-cells = <0>;
258 		compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
264 		clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
265 		power-domains = <&pd_c5>;
270 		compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
274 		clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
275 		power-domains = <&pd_a3sp>;
280 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
283 		clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
284 		power-domains = <&pd_a3sp>;
285 		#address-cells = <1>;
286 		#size-cells = <0>;
291 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
294 		clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
295 		power-domains = <&pd_a3sp>;
296 		#address-cells = <1>;
297 		#size-cells = <0>;
302 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
305 		clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
306 		power-domains = <&pd_a3sp>;
307 		#address-cells = <1>;
308 		#size-cells = <0>;
313 		compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
316 		clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
317 		power-domains = <&pd_a3sp>;
318 		#address-cells = <1>;
319 		#size-cells = <0>;
324 		compatible = "renesas,sdhi-sh73a0";
329 		clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
330 		power-domains = <&pd_a3sp>;
331 		cap-sd-highspeed;
337 		compatible = "renesas,sdhi-sh73a0";
341 		clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
342 		power-domains = <&pd_a3sp>;
343 		disable-wp;
344 		cap-sd-highspeed;
349 		compatible = "renesas,sdhi-sh73a0";
353 		clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
354 		power-domains = <&pd_a3sp>;
355 		disable-wp;
356 		cap-sd-highspeed;
361 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
364 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
365 		clock-names = "fck";
366 		power-domains = <&pd_a3sp>;
371 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
374 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
375 		clock-names = "fck";
376 		power-domains = <&pd_a3sp>;
381 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
384 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
385 		clock-names = "fck";
386 		power-domains = <&pd_a3sp>;
391 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
394 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
395 		clock-names = "fck";
396 		power-domains = <&pd_a3sp>;
401 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
404 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
405 		clock-names = "fck";
406 		power-domains = <&pd_a3sp>;
411 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
414 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
415 		clock-names = "fck";
416 		power-domains = <&pd_a3sp>;
421 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
424 		clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
425 		clock-names = "fck";
426 		power-domains = <&pd_a3sp>;
431 		compatible = "renesas,scifa-sh73a0", "renesas,scifa";
434 		clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
435 		clock-names = "fck";
436 		power-domains = <&pd_a3sp>;
441 		compatible = "renesas,scifb-sh73a0", "renesas,scifb";
444 		clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
445 		clock-names = "fck";
446 		power-domains = <&pd_a3sp>;
451 		compatible = "renesas,pfc-sh73a0";
454 		gpio-controller;
455 		#gpio-cells = <2>;
456 		gpio-ranges =
459 		interrupts-extended =
468 		power-domains = <&pd_c5>;
471 	sysc: system-controller@e6180000 {
472 		compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
475 		pm-domains {
477 				#address-cells = <1>;
478 				#size-cells = <0>;
479 				#power-domain-cells = <0>;
483 					#power-domain-cells = <0>;
488 					#power-domain-cells = <0>;
493 					#power-domain-cells = <0>;
498 					#power-domain-cells = <0>;
503 					#power-domain-cells = <0>;
508 					#power-domain-cells = <0>;
513 					#address-cells = <1>;
514 					#size-cells = <0>;
515 					#power-domain-cells = <0>;
519 						#power-domain-cells = <0>;
524 						#power-domain-cells = <0>;
530 					#address-cells = <1>;
531 					#size-cells = <0>;
532 					#power-domain-cells = <0>;
536 						#address-cells = <1>;
537 						#size-cells = <0>;
538 						#power-domain-cells = <0>;
542 							#address-cells = <1>;
543 							#size-cells = <0>;
544 							#power-domain-cells = <0>;
551 					#address-cells = <1>;
552 					#size-cells = <0>;
553 					#power-domain-cells = <0>;
557 						#power-domain-cells = <0>;
562 						#power-domain-cells = <0>;
567 						#address-cells = <1>;
568 						#size-cells = <0>;
569 						#power-domain-cells = <0>;
573 							#power-domain-cells = <0>;
582 		#sound-dai-cells = <1>;
583 		compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
586 		clocks = <&mstp3_clks SH73A0_CLK_FSI>;
587 		power-domains = <&pd_a4mp>;
592 		compatible = "renesas,bsc-sh73a0", "renesas,bsc",
593 			     "simple-pm-bus";
594 		#address-cells = <1>;
595 		#size-cells = <1>;
599 		clocks = <&zb_clk>;
600 		power-domains = <&pd_a4s>;
603 	clocks {
604 		#address-cells = <1>;
605 		#size-cells = <1>;
608 		/* External root clocks */
610 			compatible = "fixed-clock";
611 			#clock-cells = <0>;
612 			clock-frequency = <32768>;
615 			compatible = "fixed-clock";
616 			#clock-cells = <0>;
617 			clock-frequency = <26000000>;
620 			compatible = "fixed-clock";
621 			#clock-cells = <0>;
623 			clock-frequency = <0>;
626 			compatible = "fixed-clock";
627 			#clock-cells = <0>;
629 			clock-frequency = <0>;
632 			compatible = "fixed-clock";
633 			#clock-cells = <0>;
635 			clock-frequency = <0>;
638 			compatible = "fixed-clock";
639 			#clock-cells = <0>;
641 			clock-frequency = <0>;
644 		/* Special CPG clocks */
646 			compatible = "renesas,sh73a0-cpg-clocks";
648 			clocks = <&extal1_clk>, <&extal2_clk>;
649 			#clock-cells = <1>;
650 			clock-output-names = "main", "pll0", "pll1", "pll2",
656 		/* Variable factor clocks (DIV6) */
658 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
660 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
664 			#clock-cells = <0>;
667 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
669 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
673 			#clock-cells = <0>;
676 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
678 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
682 			#clock-cells = <0>;
685 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
687 			clocks = <&pll1_div2_clk>, <0>,
689 			#clock-cells = <0>;
690 			clock-output-names = "zb";
693 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
695 			clocks = <&pll1_div2_clk>, <0>,
697 			#clock-cells = <0>;
700 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
702 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
704 			#clock-cells = <0>;
707 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
709 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
711 			#clock-cells = <0>;
714 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
716 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
718 			#clock-cells = <0>;
721 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
723 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
725 			#clock-cells = <0>;
728 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
730 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
732 			#clock-cells = <0>;
735 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
737 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
739 			#clock-cells = <0>;
742 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
744 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
746 			#clock-cells = <0>;
749 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
751 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
753 			#clock-cells = <0>;
756 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
758 			clocks = <&pll1_div2_clk>, <0>,
760 			#clock-cells = <0>;
763 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
765 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
767 			#clock-cells = <0>;
770 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
772 			clocks = <&pll1_div2_clk>, <0>,
774 			#clock-cells = <0>;
777 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
779 			clocks = <&pll1_div2_clk>, <0>,
781 			#clock-cells = <0>;
784 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
786 			clocks = <&pll1_div2_clk>, <0>,
788 			#clock-cells = <0>;
791 			compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
793 			clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
796 			#clock-cells = <0>;
799 		/* Fixed factor clocks */
801 			compatible = "fixed-factor-clock";
802 			clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
803 			#clock-cells = <0>;
804 			clock-div = <2>;
805 			clock-mult = <1>;
808 			compatible = "fixed-factor-clock";
809 			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
810 			#clock-cells = <0>;
811 			clock-div = <2>;
812 			clock-mult = <1>;
815 			compatible = "fixed-factor-clock";
816 			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
817 			#clock-cells = <0>;
818 			clock-div = <7>;
819 			clock-mult = <1>;
822 			compatible = "fixed-factor-clock";
823 			clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
824 			#clock-cells = <0>;
825 			clock-div = <13>;
826 			clock-mult = <1>;
829 			compatible = "fixed-factor-clock";
830 			clocks = <&cpg_clocks SH73A0_CLK_Z>;
831 			#clock-cells = <0>;
832 			clock-div = <4>;
833 			clock-mult = <1>;
836 		/* Gate clocks */
838 			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
840 			clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
841 			#clock-cells = <1>;
842 			clock-indices = <
845 			clock-output-names =
849 			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
851 			clocks = <&cpg_clocks SH73A0_CLK_B>,
859 			#clock-cells = <1>;
860 			clock-indices = <
867 			clock-output-names =
872 			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
874 			clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
879 			#clock-cells = <1>;
880 			clock-indices = <
889 			clock-output-names =
896 			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
898 			clocks = <&sub_clk>, <&extalr_clk>,
907 			#clock-cells = <1>;
908 			clock-indices = <
918 			clock-output-names =
924 			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
926 			clocks = <&cpg_clocks SH73A0_CLK_HP>,
928 			#clock-cells = <1>;
929 			clock-indices = <
933 			clock-output-names =
937 			compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
939 			clocks = <&cpg_clocks SH73A0_CLK_HP>;
940 			#clock-cells = <1>;
941 			clock-indices = <
944 			clock-output-names =