dts/renesas/r8a7779.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 	interrupt-parent = <&gic>;
17 	#address-cells = <1>;
18 	#size-cells = <1>;
21 		#address-cells = <1>;
22 		#size-cells = <0>;
26 			compatible = "arm,cortex-a9";
28 			clock-frequency = <1000000000>;
29 			clocks = <&cpg_clocks R8A7779_CLK_Z>;
33 			compatible = "arm,cortex-a9";
35 			clock-frequency = <1000000000>;
36 			clocks = <&cpg_clocks R8A7779_CLK_Z>;
37 			power-domains = <&sysc R8A7779_PD_ARM1>;
41 			compatible = "arm,cortex-a9";
43 			clock-frequency = <1000000000>;
44 			clocks = <&cpg_clocks R8A7779_CLK_Z>;
45 			power-domains = <&sysc R8A7779_PD_ARM2>;
49 			compatible = "arm,cortex-a9";
51 			clock-frequency = <1000000000>;
52 			clocks = <&cpg_clocks R8A7779_CLK_Z>;
53 			power-domains = <&sysc R8A7779_PD_ARM3>;
63 	gic: interrupt-controller@f0001000 {
64 		compatible = "arm,cortex-a9-gic";
65 		#interrupt-cells = <3>;
66 		interrupt-controller;
72 		compatible = "arm,cortex-a9-global-timer";
76 		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
80 		compatible = "arm,cortex-a9-twd-timer";
84 		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
88 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
91 		#gpio-cells = <2>;
92 		gpio-controller;
93 		gpio-ranges = <&pfc 0 0 32>;
94 		#interrupt-cells = <2>;
95 		interrupt-controller;
99 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
102 		#gpio-cells = <2>;
103 		gpio-controller;
104 		gpio-ranges = <&pfc 0 32 32>;
105 		#interrupt-cells = <2>;
106 		interrupt-controller;
110 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
113 		#gpio-cells = <2>;
114 		gpio-controller;
115 		gpio-ranges = <&pfc 0 64 32>;
116 		#interrupt-cells = <2>;
117 		interrupt-controller;
121 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
124 		#gpio-cells = <2>;
125 		gpio-controller;
126 		gpio-ranges = <&pfc 0 96 32>;
127 		#interrupt-cells = <2>;
128 		interrupt-controller;
132 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
135 		#gpio-cells = <2>;
136 		gpio-controller;
137 		gpio-ranges = <&pfc 0 128 32>;
138 		#interrupt-cells = <2>;
139 		interrupt-controller;
143 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
146 		#gpio-cells = <2>;
147 		gpio-controller;
148 		gpio-ranges = <&pfc 0 160 32>;
149 		#interrupt-cells = <2>;
150 		interrupt-controller;
154 		compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
157 		#gpio-cells = <2>;
158 		gpio-controller;
159 		gpio-ranges = <&pfc 0 192 9>;
160 		#interrupt-cells = <2>;
161 		interrupt-controller;
164 	irqpin0: interrupt-controller@fe78001c {
165 		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
166 		#interrupt-cells = <2>;
168 		interrupt-controller;
179 		sense-bitfield-width = <2>;
183 		#address-cells = <1>;
184 		#size-cells = <0>;
185 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
188 		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
189 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
194 		#address-cells = <1>;
195 		#size-cells = <0>;
196 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
199 		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
200 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
201 		i2c-scl-internal-delay-ns = <5>;
206 		#address-cells = <1>;
207 		#size-cells = <0>;
208 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
211 		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
212 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
213 		i2c-scl-internal-delay-ns = <5>;
218 		#address-cells = <1>;
219 		#size-cells = <0>;
220 		compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
223 		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
224 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
225 		i2c-scl-internal-delay-ns = <5>;
230 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
234 		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
236 		clock-names = "fck", "brg_int", "scif_clk";
237 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
242 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
246 		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
248 		clock-names = "fck", "brg_int", "scif_clk";
249 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
254 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
258 		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
260 		clock-names = "fck", "brg_int", "scif_clk";
261 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
266 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
270 		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
272 		clock-names = "fck", "brg_int", "scif_clk";
273 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
278 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
282 		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
284 		clock-names = "fck", "brg_int", "scif_clk";
285 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
290 		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
294 		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
296 		clock-names = "fck", "brg_int", "scif_clk";
297 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
302 		compatible = "renesas,hscif-r8a7779",
303 			     "renesas,rcar-gen1-hscif", "renesas,hscif";
306 		clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
309 		clock-names = "fck", "brg_int", "scif_clk";
310 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
315 		compatible = "renesas,hscif-r8a7779",
316 			     "renesas,rcar-gen1-hscif", "renesas,hscif";
319 		clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
322 		clock-names = "fck", "brg_int", "scif_clk";
323 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
328 		compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
330 		clocks = <&mstp0_clks R8A7779_CLK_PWM>;
331 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
332 		#pwm-cells = <2>;
337 		compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
339 		clocks = <&mstp0_clks R8A7779_CLK_PWM>;
340 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
341 		#pwm-cells = <2>;
346 		compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
348 		clocks = <&mstp0_clks R8A7779_CLK_PWM>;
349 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
350 		#pwm-cells = <2>;
355 		compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
357 		clocks = <&mstp0_clks R8A7779_CLK_PWM>;
358 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
359 		#pwm-cells = <2>;
364 		compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
366 		clocks = <&mstp0_clks R8A7779_CLK_PWM>;
367 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
368 		#pwm-cells = <2>;
373 		compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
375 		clocks = <&mstp0_clks R8A7779_CLK_PWM>;
376 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
377 		#pwm-cells = <2>;
382 		compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar";
384 		clocks = <&mstp0_clks R8A7779_CLK_PWM>;
385 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
386 		#pwm-cells = <2>;
391 		compatible = "renesas,pfc-r8a7779";
396 		compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
401 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
407 		interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
408 		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
409 		clock-names = "fck";
410 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
418 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
424 		interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
425 		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
426 		clock-names = "fck";
427 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
435 		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
440 		interrupt-names = "tuni0", "tuni1", "tuni2";
441 		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
442 		clock-names = "fck";
443 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
451 		compatible = "renesas,sata-r8a7779";
454 		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
455 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
460 		compatible = "renesas,sdhi-r8a7779",
461 			     "renesas,rcar-gen1-sdhi";
464 		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
465 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
470 		compatible = "renesas,sdhi-r8a7779",
471 			     "renesas,rcar-gen1-sdhi";
474 		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
475 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
480 		compatible = "renesas,sdhi-r8a7779",
481 			     "renesas,rcar-gen1-sdhi";
484 		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
485 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
490 		compatible = "renesas,sdhi-r8a7779",
491 			     "renesas,rcar-gen1-sdhi";
494 		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
495 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
500 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
503 		#address-cells = <1>;
504 		#size-cells = <0>;
505 		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
506 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
511 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
514 		#address-cells = <1>;
515 		#size-cells = <0>;
516 		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
517 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
522 		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
525 		#address-cells = <1>;
526 		#size-cells = <0>;
527 		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
528 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
533 		compatible = "renesas,du-r8a7779";
536 		clocks = <&mstp1_clks R8A7779_CLK_DU>;
537 		clock-names = "du.0";
538 		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
542 			#address-cells = <1>;
543 			#size-cells = <0>;
558 	clocks {
559 		#address-cells = <1>;
560 		#size-cells = <1>;
565 			compatible = "fixed-clock";
566 			#clock-cells = <0>;
568 			clock-frequency = <0>;
573 			compatible = "fixed-clock";
574 			#clock-cells = <0>;
576 			clock-frequency = <0>;
579 		/* Special CPG clocks */
580 		cpg_clocks: clocks@ffc80000 {
581 			compatible = "renesas,r8a7779-cpg-clocks";
583 			clocks = <&extal_clk>;
584 			#clock-cells = <1>;
585 			clock-output-names = "plla", "z", "zs", "s",
587 			#power-domain-cells = <0>;
590 		/* Fixed factor clocks */
592 			compatible = "fixed-factor-clock";
593 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
594 			#clock-cells = <0>;
595 			clock-div = <2>;
596 			clock-mult = <1>;
599 			compatible = "fixed-factor-clock";
600 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
601 			#clock-cells = <0>;
602 			clock-div = <8>;
603 			clock-mult = <1>;
606 			compatible = "fixed-factor-clock";
607 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
608 			#clock-cells = <0>;
609 			clock-div = <16>;
610 			clock-mult = <1>;
613 			compatible = "fixed-factor-clock";
614 			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
615 			#clock-cells = <0>;
616 			clock-div = <24>;
617 			clock-mult = <1>;
620 		/* Gate clocks */
621 		mstp0_clks: clocks@ffc80030 {
622 			compatible = "renesas,r8a7779-mstp-clocks",
623 				     "renesas,cpg-mstp-clocks";
625 			clocks = <&cpg_clocks R8A7779_CLK_P>,
642 			#clock-cells = <1>;
643 			clock-indices = <
654 			clock-output-names =
660 		mstp1_clks: clocks@ffc80034 {
661 			compatible = "renesas,r8a7779-mstp-clocks",
662 				     "renesas,cpg-mstp-clocks";
664 			clocks = <&cpg_clocks R8A7779_CLK_P>,
674 			#clock-cells = <1>;
675 			clock-indices = <
682 			clock-output-names =
689 		mstp3_clks: clocks@ffc8003c {
690 			compatible = "renesas,r8a7779-mstp-clocks",
691 				     "renesas,cpg-mstp-clocks";
693 			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
695 			#clock-cells = <1>;
696 			clock-indices = <
701 			clock-output-names =
708 		compatible = "simple-bus";
709 		#address-cells = <1>;
710 		#size-cells = <1>;
719 	rst: reset-controller@ffcc0000 {
720 		compatible = "renesas,r8a7779-reset-wdt";
724 	sysc: system-controller@ffd85000 {
725 		compatible = "renesas,r8a7779-sysc";
727 		#power-domain-cells = <1>;