dts/renesas/r8a7778.dtsi

1 // SPDX-License-Identifier: GPL-2.0
3  * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 	interrupt-parent = <&gic>;
21 	#address-cells = <1>;
22 	#size-cells = <1>;
25 		#address-cells = <1>;
26 		#size-cells = <0>;
30 			compatible = "arm,cortex-a9";
32 			clock-frequency = <800000000>;
33 			clocks = <&z_clk>;
44 		compatible = "simple-bus";
45 		#address-cells = <1>;
46 		#size-cells = <1>;
51 		compatible = "renesas,ether-r8a7778",
52 			     "renesas,rcar-gen1-ether";
55 		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
56 		power-domains = <&cpg_clocks>;
57 		phy-mode = "rmii";
58 		#address-cells = <1>;
59 		#size-cells = <0>;
63 	gic: interrupt-controller@fe438000 {
65 		#interrupt-cells = <3>;
66 		interrupt-controller;
71 	/* irqpin: IRQ0 - IRQ3 */
72 	irqpin: interrupt-controller@fe78001c {
73 		compatible = "renesas,intc-irqpin-r8a7778", "renesas,intc-irqpin";
74 		#interrupt-cells = <2>;
75 		interrupt-controller;
87 		sense-bitfield-width = <2>;
91 		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
94 		#gpio-cells = <2>;
95 		gpio-controller;
96 		gpio-ranges = <&pfc 0 0 32>;
97 		#interrupt-cells = <2>;
98 		interrupt-controller;
102 		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
105 		#gpio-cells = <2>;
106 		gpio-controller;
107 		gpio-ranges = <&pfc 0 32 32>;
108 		#interrupt-cells = <2>;
109 		interrupt-controller;
113 		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
116 		#gpio-cells = <2>;
117 		gpio-controller;
118 		gpio-ranges = <&pfc 0 64 32>;
119 		#interrupt-cells = <2>;
120 		interrupt-controller;
124 		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
127 		#gpio-cells = <2>;
128 		gpio-controller;
129 		gpio-ranges = <&pfc 0 96 32>;
130 		#interrupt-cells = <2>;
131 		interrupt-controller;
135 		compatible = "renesas,gpio-r8a7778", "renesas,rcar-gen1-gpio";
138 		#gpio-cells = <2>;
139 		gpio-controller;
140 		gpio-ranges = <&pfc 0 128 27>;
141 		#interrupt-cells = <2>;
142 		interrupt-controller;
146 		compatible = "renesas,pfc-r8a7778";
151 		#address-cells = <1>;
152 		#size-cells = <0>;
153 		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
156 		clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
157 		power-domains = <&cpg_clocks>;
162 		#address-cells = <1>;
163 		#size-cells = <0>;
164 		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
167 		clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
168 		power-domains = <&cpg_clocks>;
169 		i2c-scl-internal-delay-ns = <5>;
174 		#address-cells = <1>;
175 		#size-cells = <0>;
176 		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
179 		clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
180 		power-domains = <&cpg_clocks>;
181 		i2c-scl-internal-delay-ns = <5>;
186 		#address-cells = <1>;
187 		#size-cells = <0>;
188 		compatible = "renesas,i2c-r8a7778", "renesas,rcar-gen1-i2c";
191 		clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
192 		power-domains = <&cpg_clocks>;
193 		i2c-scl-internal-delay-ns = <5>;
198 		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
204 		interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
205 		clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
206 		clock-names = "fck";
207 		power-domains = <&cpg_clocks>;
215 		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
221 		interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
222 		clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
223 		clock-names = "fck";
224 		power-domains = <&cpg_clocks>;
232 		compatible = "renesas,tmu-r8a7778", "renesas,tmu";
237 		interrupt-names = "tuni0", "tuni1", "tuni2";
238 		clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
239 		clock-names = "fck";
240 		power-domains = <&cpg_clocks>;
249 		 * #sound-dai-cells is required if simple-card
251 		 * Single DAI : #sound-dai-cells = <0>;         <&rcar_sound>;
252 		 * Multi  DAI : #sound-dai-cells = <1>;         <&rcar_sound N>;
254 		compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
258 		reg-names = "sru", "ssi", "adg";
260 		clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
280 		clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
289 			src3: src-3 { };
290 			src4: src-4 { };
291 			src5: src-5 { };
292 			src6: src-6 { };
293 			src7: src-7 { };
294 			src8: src-8 { };
295 			src9: src-9 { };
299 			ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
300 			ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
301 			ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
302 			ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
303 			ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
304 			ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
305 			ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
310 		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
314 		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
316 		clock-names = "fck", "brg_int", "scif_clk";
317 		power-domains = <&cpg_clocks>;
322 		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
326 		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
328 		clock-names = "fck", "brg_int", "scif_clk";
329 		power-domains = <&cpg_clocks>;
334 		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
338 		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
340 		clock-names = "fck", "brg_int", "scif_clk";
341 		power-domains = <&cpg_clocks>;
346 		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
350 		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
352 		clock-names = "fck", "brg_int", "scif_clk";
353 		power-domains = <&cpg_clocks>;
358 		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
362 		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
364 		clock-names = "fck", "brg_int", "scif_clk";
365 		power-domains = <&cpg_clocks>;
370 		compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
374 		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
376 		clock-names = "fck", "brg_int", "scif_clk";
377 		power-domains = <&cpg_clocks>;
382 		compatible = "renesas,hscif-r8a7778",
383 			     "renesas,rcar-gen1-hscif", "renesas,hscif";
386 		clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
388 		clock-names = "fck", "brg_int", "scif_clk";
389 		power-domains = <&cpg_clocks>;
394 		compatible = "renesas,hscif-r8a7778",
395 			     "renesas,rcar-gen1-hscif", "renesas,hscif";
398 		clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
400 		clock-names = "fck", "brg_int", "scif_clk";
401 		power-domains = <&cpg_clocks>;
406 		compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
409 		clocks = <&mstp3_clks R8A7778_CLK_MMC>;
410 		power-domains = <&cpg_clocks>;
415 		compatible = "renesas,sdhi-r8a7778",
416 			     "renesas,rcar-gen1-sdhi";
419 		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
420 		power-domains = <&cpg_clocks>;
425 		compatible = "renesas,sdhi-r8a7778",
426 			     "renesas,rcar-gen1-sdhi";
429 		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
430 		power-domains = <&cpg_clocks>;
435 		compatible = "renesas,sdhi-r8a7778",
436 			     "renesas,rcar-gen1-sdhi";
439 		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
440 		power-domains = <&cpg_clocks>;
445 		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
448 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
449 		power-domains = <&cpg_clocks>;
450 		#address-cells = <1>;
451 		#size-cells = <0>;
456 		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
459 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
460 		power-domains = <&cpg_clocks>;
461 		#address-cells = <1>;
462 		#size-cells = <0>;
467 		compatible = "renesas,hspi-r8a7778", "renesas,hspi";
470 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
471 		power-domains = <&cpg_clocks>;
472 		#address-cells = <1>;
473 		#size-cells = <0>;
477 	clocks {
478 		#address-cells = <1>;
479 		#size-cells = <1>;
484 			compatible = "fixed-clock";
485 			#clock-cells = <0>;
486 			clock-frequency = <0>;
491 			compatible = "fixed-clock";
492 			#clock-cells = <0>;
494 			clock-frequency = <0>;
497 		/* Special CPG clocks */
499 			compatible = "renesas,r8a7778-cpg-clocks";
501 			#clock-cells = <1>;
502 			clocks = <&extal_clk>;
503 			clock-output-names = "plla", "pllb", "b",
505 			#power-domain-cells = <0>;
508 		/* Audio clocks; frequencies are set by boards if applicable. */
510 			compatible = "fixed-clock";
511 			#clock-cells = <0>;
512 			clock-frequency = <0>;
515 			compatible = "fixed-clock";
516 			#clock-cells = <0>;
517 			clock-frequency = <0>;
520 			compatible = "fixed-clock";
521 			#clock-cells = <0>;
522 			clock-frequency = <0>;
525 		/* Fixed ratio clocks */
527 			compatible = "fixed-factor-clock";
528 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
529 			#clock-cells = <0>;
530 			clock-div = <12>;
531 			clock-mult = <1>;
534 			compatible = "fixed-factor-clock";
535 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
536 			#clock-cells = <0>;
537 			clock-div = <1>;
538 			clock-mult = <1>;
541 			compatible = "fixed-factor-clock";
542 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
543 			#clock-cells = <0>;
544 			clock-div = <4>;
545 			clock-mult = <1>;
548 			compatible = "fixed-factor-clock";
549 			clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
550 			#clock-cells = <0>;
551 			clock-div = <8>;
552 			clock-mult = <1>;
555 			compatible = "fixed-factor-clock";
556 			clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
557 			#clock-cells = <0>;
558 			clock-div = <1>;
559 			clock-mult = <1>;
562 		/* Gate clocks */
564 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
566 			clocks = <&cpg_clocks R8A7778_CLK_P>,
587 			#clock-cells = <1>;
588 			clock-indices = <
601 			clock-output-names =
609 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
611 			clocks = <&cpg_clocks R8A7778_CLK_P>,
615 			#clock-cells = <1>;
616 			clock-indices = <
620 			clock-output-names =
624 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
626 			clocks = <&s4_clk>,
635 			#clock-cells = <1>;
636 			clock-indices = <
643 			clock-output-names =
648 			compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
650 			clocks = <&cpg_clocks R8A7778_CLK_P>,
659 			#clock-cells = <1>;
660 			clock-indices = <
667 			clock-output-names =
668 				"sru-src0", "sru-src1", "sru-src2",
669 				"sru-src3", "sru-src4", "sru-src5",
670 				"sru-src6", "sru-src7", "sru-src8";
674 	rst: reset-controller@ffcc0000 {
675 		compatible = "renesas,r8a7778-reset-wdt";