Lines Matching +full:0 +full:x7000d600
21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
60 pci@1,0 {
62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
63 reg = <0x000800 0 0 0 0>;
64 bus-range = <0x00 0xff>;
74 pci@2,0 {
76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
77 reg = <0x001000 0 0 0 0>;
78 bus-range = <0x00 0xff>;
91 reg = <0x0 0x50000000 0x0 0x00034000>;
104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
108 reg = <0x0 0x54200000 0x0 0x00040000>;
117 nvidia,head = <0>;
135 reg = <0x0 0x54240000 0x0 0x00040000>;
158 reg = <0x0 0x54280000 0x0 0x00040000>;
170 reg = <0x0 0x54300000 0x0 0x00040000>;
177 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
181 #size-cells = <0>;
186 reg = <0x0 0x54340000 0x0 0x00040000>;
198 reg = <0x0 0x54400000 0x0 0x00040000>;
205 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
209 #size-cells = <0>;
214 reg = <0x0 0x54540000 0x0 0x00040000>;
229 reg = <0x0 0x545c0000 0x0 0x00040000>;
240 #size-cells = <0>;
249 reg = <0x0 0x50041000 0x0 0x1000>,
250 <0x0 0x50042000 0x0 0x1000>,
251 <0x0 0x50044000 0x0 0x2000>,
252 <0x0 0x50046000 0x0 0x2000>;
260 reg = <0x0 0x57000000 0x0 0x01000000>,
261 <0x0 0x58000000 0x0 0x01000000>;
278 reg = <0x0 0x60004000 0x0 0x100>,
279 <0x0 0x60004100 0x0 0x100>,
280 <0x0 0x60004200 0x0 0x100>,
281 <0x0 0x60004300 0x0 0x100>,
282 <0x0 0x60004400 0x0 0x100>;
290 reg = <0x0 0x60005000 0x0 0x400>;
291 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
302 reg = <0x0 0x60006000 0x0 0x1000>;
310 reg = <0x0 0x60007000 0x0 0x1000>;
315 reg = <0x0 0x6000c800 0x0 0x400>;
330 reg = <0x0 0x6000d000 0x0 0x1000>;
343 gpio-ranges = <&pinmux 0 0 251>;
348 reg = <0x0 0x60020000 0x0 0x1400>;
389 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
390 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
395 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
396 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
397 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
410 reg = <0x0 0x70006000 0x0 0x40>;
422 reg = <0x0 0x70006040 0x0 0x40>;
434 reg = <0x0 0x70006200 0x0 0x40>;
446 reg = <0x0 0x70006300 0x0 0x40>;
458 reg = <0x0 0x7000a000 0x0 0x100>;
468 reg = <0x0 0x7000c000 0x0 0x100>;
471 #size-cells = <0>;
483 reg = <0x0 0x7000c400 0x0 0x100>;
486 #size-cells = <0>;
498 reg = <0x0 0x7000c500 0x0 0x100>;
501 #size-cells = <0>;
513 reg = <0x0 0x7000c700 0x0 0x100>;
516 #size-cells = <0>;
528 reg = <0x0 0x7000d000 0x0 0x100>;
531 #size-cells = <0>;
543 reg = <0x0 0x7000d100 0x0 0x100>;
546 #size-cells = <0>;
558 reg = <0x0 0x7000d400 0x0 0x200>;
561 #size-cells = <0>;
573 reg = <0x0 0x7000d600 0x0 0x200>;
576 #size-cells = <0>;
588 reg = <0x0 0x7000d800 0x0 0x200>;
591 #size-cells = <0>;
603 reg = <0x0 0x7000da00 0x0 0x200>;
606 #size-cells = <0>;
618 reg = <0x0 0x7000dc00 0x0 0x200>;
621 #size-cells = <0>;
633 reg = <0x0 0x7000de00 0x0 0x200>;
636 #size-cells = <0>;
648 reg = <0x0 0x7000e000 0x0 0x100>;
655 reg = <0x0 0x7000e400 0x0 0x400>;
663 reg = <0x0 0x7000f800 0x0 0x400>;
672 reg = <0x0 0x70015000 0x0 0x00001000>;
682 reg = <0x0 0x70019000 0x0 0x1000>;
695 reg = <0x0 0x7001b000 0x0 0x1000>;
702 #interconnect-cells = <0>;
707 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
708 <0x0 0x70020000 0x0 0x7000>; /* SATA */
722 reg = <0x0 0x70030000 0x0 0x10000>;
737 reg = <0x0 0x70090000 0x0 0x8000>,
738 <0x0 0x70098000 0x0 0x1000>,
739 <0x0 0x70099000 0x0 0x1000>;
772 reg = <0x0 0x7009f000 0x0 0x1000>;
781 usb2-0 {
783 #phy-cells = <0>;
788 #phy-cells = <0>;
793 #phy-cells = <0>;
802 ulpi-0 {
804 #phy-cells = <0>;
813 hsic-0 {
815 #phy-cells = <0>;
820 #phy-cells = <0>;
829 pcie-0 {
831 #phy-cells = <0>;
836 #phy-cells = <0>;
841 #phy-cells = <0>;
846 #phy-cells = <0>;
851 #phy-cells = <0>;
860 sata-0 {
862 #phy-cells = <0>;
869 usb2-0 {
881 ulpi-0 {
885 hsic-0 {
893 usb3-0 {
905 reg = <0x0 0x700b0000 0x0 0x200>;
916 reg = <0x0 0x700b0200 0x0 0x200>;
927 reg = <0x0 0x700b0400 0x0 0x200>;
938 reg = <0x0 0x700b0600 0x0 0x200>;
949 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
950 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
975 reg = <0x0 0x700e3000 0x0 0x100>;
983 reg = <0 0x70110000 0 0x100>, /* DFLL control */
984 <0 0x70110000 0 0x100>, /* I2C output control */
985 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
986 <0 0x70110200 0 0x100>; /* Look-up table RAM */
994 #clock-cells = <0>;
997 nvidia,droop-ctrl = <0x00000f00>;
1000 nvidia,ci = <0>;
1007 reg = <0x0 0x70300000 0x0 0x200>,
1008 <0x0 0x70300800 0x0 0x800>,
1009 <0x0 0x70300200 0x0 0x600>;
1059 reg = <0x0 0x70301000 0x0 0x100>;
1069 reg = <0x0 0x70301100 0x0 0x100>;
1079 reg = <0x0 0x70301200 0x0 0x100>;
1089 reg = <0x0 0x70301300 0x0 0x100>;
1099 reg = <0x0 0x70301400 0x0 0x100>;
1110 reg = <0x0 0x7d000000 0x0 0x4000>;
1122 reg = <0x0 0x7d000000 0x0 0x4000>,
1123 <0x0 0x7d000000 0x0 0x4000>;
1132 #phy-cells = <0>;
1133 nvidia,hssync-start-delay = <0>;
1138 nvidia,xcvr-lsfslew = <0>;
1144 nvidia,pmc = <&tegra_pmc 0>;
1150 reg = <0x0 0x7d004000 0x0 0x4000>;
1162 reg = <0x0 0x7d004000 0x0 0x4000>,
1163 <0x0 0x7d000000 0x0 0x4000>;
1172 #phy-cells = <0>;
1173 nvidia,hssync-start-delay = <0>;
1178 nvidia,xcvr-lsfslew = <0>;
1189 reg = <0x0 0x7d008000 0x0 0x4000>;
1201 reg = <0x0 0x7d008000 0x0 0x4000>,
1202 <0x0 0x7d000000 0x0 0x4000>;
1211 #phy-cells = <0>;
1212 nvidia,hssync-start-delay = <0>;
1217 nvidia,xcvr-lsfslew = <0>;
1228 #size-cells = <0>;
1230 cpu@0 {
1233 reg = <0>;
1270 interrupt-affinity = <&{/cpus/cpu@0}>,
1287 hysteresis = <0>;
1315 hysteresis = <0>;
1343 hysteresis = <0>;
1371 hysteresis = <0>;