Lines Matching +full:reg +full:- +full:names
2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
55 #address-cells = <2>;
56 #size-cells = <2>;
57 interrupt-parent = <&gic>;
64 #address-cells = <1>;
65 #size-cells = <0>;
68 compatible = "arm,cortex-a7";
70 cci-control-port = <&cci_control0>;
71 clock-frequency = <12000000>;
72 enable-method = "allwinner,sun9i-a80-smp";
73 reg = <0x0>;
77 compatible = "arm,cortex-a7";
79 cci-control-port = <&cci_control0>;
80 clock-frequency = <12000000>;
81 enable-method = "allwinner,sun9i-a80-smp";
82 reg = <0x1>;
86 compatible = "arm,cortex-a7";
88 cci-control-port = <&cci_control0>;
89 clock-frequency = <12000000>;
90 enable-method = "allwinner,sun9i-a80-smp";
91 reg = <0x2>;
95 compatible = "arm,cortex-a7";
97 cci-control-port = <&cci_control0>;
98 clock-frequency = <12000000>;
99 enable-method = "allwinner,sun9i-a80-smp";
100 reg = <0x3>;
104 compatible = "arm,cortex-a15";
106 cci-control-port = <&cci_control1>;
107 clock-frequency = <18000000>;
108 enable-method = "allwinner,sun9i-a80-smp";
109 reg = <0x100>;
113 compatible = "arm,cortex-a15";
115 cci-control-port = <&cci_control1>;
116 clock-frequency = <18000000>;
117 enable-method = "allwinner,sun9i-a80-smp";
118 reg = <0x101>;
122 compatible = "arm,cortex-a15";
124 cci-control-port = <&cci_control1>;
125 clock-frequency = <18000000>;
126 enable-method = "allwinner,sun9i-a80-smp";
127 reg = <0x102>;
131 compatible = "arm,cortex-a15";
133 cci-control-port = <&cci_control1>;
134 clock-frequency = <18000000>;
135 enable-method = "allwinner,sun9i-a80-smp";
136 reg = <0x103>;
141 compatible = "arm,armv7-timer";
146 clock-frequency = <24000000>;
147 arm,cpu-registers-not-fw-configured;
151 #address-cells = <1>;
152 #size-cells = <1>;
170 osc24M: clk-24M {
171 #clock-cells = <0>;
172 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "osc24M";
182 osc32k: clk-32k {
183 #clock-cells = <0>;
184 compatible = "fixed-factor-clock";
185 clock-div = <1>;
186 clock-mult = <1>;
187 clock-output-names = "osc32k";
194 * mode, using clk_set_rate auto-reparenting.
199 mii_phy_tx_clk: mii-phy-tx-clk {
200 #clock-cells = <0>;
201 compatible = "fixed-clock";
202 clock-frequency = <25000000>;
203 clock-output-names = "mii_phy_tx";
206 gmac_int_tx_clk: gmac-int-tx-clk {
207 #clock-cells = <0>;
208 compatible = "fixed-clock";
209 clock-frequency = <125000000>;
210 clock-output-names = "gmac_int_tx";
214 #clock-cells = <0>;
215 compatible = "allwinner,sun7i-a20-gmac-clk";
216 reg = <0x00800030 0x4>;
218 clock-output-names = "gmac_tx";
222 compatible = "allwinner,sun9i-a80-cpus-clk";
223 reg = <0x08001410 0x4>;
224 #clock-cells = <0>;
228 clock-output-names = "cpus";
231 ahbs: clk-ahbs {
232 compatible = "fixed-factor-clock";
233 #clock-cells = <0>;
234 clock-div = <1>;
235 clock-mult = <1>;
237 clock-output-names = "ahbs";
241 compatible = "allwinner,sun8i-a23-apb0-clk";
242 reg = <0x0800141c 0x4>;
243 #clock-cells = <0>;
245 clock-output-names = "apbs";
249 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
250 reg = <0x08001428 0x4>;
251 #clock-cells = <1>;
253 clock-indices = <0>, <1>,
260 clock-output-names = "apbs_pio", "apbs_ir",
270 reg = <0x08001450 0x4>;
271 #clock-cells = <0>;
272 compatible = "allwinner,sun4i-a10-mod0-clk";
274 clock-output-names = "r_1wire";
278 reg = <0x08001454 0x4>;
279 #clock-cells = <0>;
280 compatible = "allwinner,sun4i-a10-mod0-clk";
282 clock-output-names = "r_ir";
286 de: display-engine {
287 compatible = "allwinner,sun9i-a80-display-engine";
293 compatible = "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
304 compatible = "mmio-sram";
305 reg = <0x00020000 0x40000>;
307 #address-cells = <1>;
308 #size-cells = <1>;
311 smp-sram@1000 {
316 compatible = "allwinner,sun9i-a80-smp-sram";
317 reg = <0x1000 0x8>;
322 compatible = "allwinner,sun7i-a20-gmac";
323 reg = <0x00830000 0x1054>;
325 interrupt-names = "macirq";
327 clock-names = "stmmaceth", "allwinner_gmac_tx";
329 reset-names = "stmmaceth";
331 snps,fixed-burst;
336 compatible = "snps,dwmac-mdio";
337 #address-cells = <1>;
338 #size-cells = <0>;
343 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
344 reg = <0x00a00000 0x100>;
349 phy-names = "usb";
354 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
355 reg = <0x00a00400 0x100>;
361 phy-names = "usb";
366 compatible = "allwinner,sun9i-a80-usb-phy";
367 reg = <0x00a00800 0x4>;
369 clock-names = "phy";
371 reset-names = "phy";
373 #phy-cells = <0>;
377 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
378 reg = <0x00a01000 0x100>;
383 phy-names = "usb";
388 compatible = "allwinner,sun9i-a80-usb-phy";
389 reg = <0x00a01800 0x4>;
393 clock-names = "phy",
398 reset-names = "phy",
401 #phy-cells = <0>;
407 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
408 reg = <0x00a02000 0x100>;
413 phy-names = "usb";
418 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
419 reg = <0x00a02400 0x100>;
425 phy-names = "usb";
430 compatible = "allwinner,sun9i-a80-usb-phy";
431 reg = <0x00a02800 0x4>;
435 clock-names = "phy",
440 reset-names = "phy",
443 #phy-cells = <0>;
447 compatible = "allwinner,sun9i-a80-usb-clks";
448 reg = <0x00a08000 0x8>;
450 clock-names = "bus", "hosc";
451 #clock-cells = <1>;
452 #reset-cells = <1>;
456 compatible = "allwinner,sun9i-a80-cpucfg";
457 reg = <0x01700000 0x100>;
461 compatible = "allwinner,sun9i-a80-crypto";
462 reg = <0x01c02000 0x1000>;
466 clock-names = "bus", "mod";
470 compatible = "allwinner,sun9i-a80-mmc";
471 reg = <0x01c0f000 0x1000>;
475 clock-names = "ahb", "mmc", "output", "sample";
477 reset-names = "ahb";
480 #address-cells = <1>;
481 #size-cells = <0>;
485 compatible = "allwinner,sun9i-a80-mmc";
486 reg = <0x01c10000 0x1000>;
490 clock-names = "ahb", "mmc", "output", "sample";
492 reset-names = "ahb";
495 #address-cells = <1>;
496 #size-cells = <0>;
500 compatible = "allwinner,sun9i-a80-mmc";
501 reg = <0x01c11000 0x1000>;
505 clock-names = "ahb", "mmc", "output", "sample";
507 reset-names = "ahb";
510 #address-cells = <1>;
511 #size-cells = <0>;
515 compatible = "allwinner,sun9i-a80-mmc";
516 reg = <0x01c12000 0x1000>;
520 clock-names = "ahb", "mmc", "output", "sample";
522 reset-names = "ahb";
525 #address-cells = <1>;
526 #size-cells = <0>;
530 compatible = "allwinner,sun9i-a80-mmc-config-clk";
531 reg = <0x01c13000 0x10>;
534 #clock-cells = <1>;
535 #reset-cells = <1>;
536 clock-output-names = "mmc0_config", "mmc1_config",
540 gic: interrupt-controller@1c41000 {
541 compatible = "arm,gic-400";
542 reg = <0x01c41000 0x1000>,
546 interrupt-controller;
547 #interrupt-cells = <3>;
552 compatible = "arm,cci-400";
553 #address-cells = <1>;
554 #size-cells = <1>;
555 reg = <0x01c90000 0x1000>;
558 cci_control0: slave-if@4000 {
559 compatible = "arm,cci-400-ctrl-if";
560 interface-type = "ace";
561 reg = <0x4000 0x1000>;
564 cci_control1: slave-if@5000 {
565 compatible = "arm,cci-400-ctrl-if";
566 interface-type = "ace";
567 reg = <0x5000 0x1000>;
571 compatible = "arm,cci-400-pmu,r1";
572 reg = <0x9000 0x5000>;
582 compatible = "allwinner,sun9i-a80-de-clks";
583 reg = <0x03000000 0x30>;
587 clock-names = "mod",
591 #clock-cells = <1>;
592 #reset-cells = <1>;
595 fe0: display-frontend@3100000 {
596 compatible = "allwinner,sun9i-a80-display-frontend";
597 reg = <0x03100000 0x40000>;
601 clock-names = "ahb", "mod",
606 #address-cells = <1>;
607 #size-cells = <0>;
610 reg = <1>;
613 remote-endpoint = <&deu0_in_fe0>;
619 fe1: display-frontend@3140000 {
620 compatible = "allwinner,sun9i-a80-display-frontend";
621 reg = <0x03140000 0x40000>;
625 clock-names = "ahb", "mod",
630 #address-cells = <1>;
631 #size-cells = <0>;
634 reg = <1>;
637 remote-endpoint = <&deu1_in_fe1>;
643 be0: display-backend@3200000 {
644 compatible = "allwinner,sun9i-a80-display-backend";
645 reg = <0x03200000 0x40000>;
649 clock-names = "ahb", "mod",
654 #address-cells = <1>;
655 #size-cells = <0>;
658 #address-cells = <1>;
659 #size-cells = <0>;
660 reg = <0>;
663 reg = <0>;
664 remote-endpoint = <&deu0_out_be0>;
668 reg = <1>;
669 remote-endpoint = <&deu1_out_be0>;
674 reg = <1>;
677 remote-endpoint = <&drc0_in_be0>;
683 be1: display-backend@3240000 {
684 compatible = "allwinner,sun9i-a80-display-backend";
685 reg = <0x03240000 0x40000>;
689 clock-names = "ahb", "mod",
694 #address-cells = <1>;
695 #size-cells = <0>;
698 #address-cells = <1>;
699 #size-cells = <0>;
700 reg = <0>;
703 reg = <0>;
704 remote-endpoint = <&deu0_out_be1>;
708 reg = <1>;
709 remote-endpoint = <&deu1_out_be1>;
714 reg = <1>;
717 remote-endpoint = <&drc1_in_be1>;
724 compatible = "allwinner,sun9i-a80-deu";
725 reg = <0x03300000 0x40000>;
730 clock-names = "ahb",
736 #address-cells = <1>;
737 #size-cells = <0>;
740 reg = <0>;
743 remote-endpoint = <&fe0_out_deu0>;
748 #address-cells = <1>;
749 #size-cells = <0>;
750 reg = <1>;
753 reg = <0>;
754 remote-endpoint = <&be0_in_deu0>;
758 reg = <1>;
759 remote-endpoint = <&be1_in_deu0>;
766 compatible = "allwinner,sun9i-a80-deu";
767 reg = <0x03340000 0x40000>;
772 clock-names = "ahb",
778 #address-cells = <1>;
779 #size-cells = <0>;
782 reg = <0>;
785 remote-endpoint = <&fe1_out_deu1>;
790 #address-cells = <1>;
791 #size-cells = <0>;
792 reg = <1>;
795 reg = <0>;
796 remote-endpoint = <&be0_in_deu1>;
800 reg = <1>;
801 remote-endpoint = <&be1_in_deu1>;
808 compatible = "allwinner,sun9i-a80-drc";
809 reg = <0x03400000 0x40000>;
814 clock-names = "ahb",
820 #address-cells = <1>;
821 #size-cells = <0>;
824 reg = <0>;
827 remote-endpoint = <&be0_out_drc0>;
832 reg = <1>;
835 remote-endpoint = <&tcon0_in_drc0>;
842 compatible = "allwinner,sun9i-a80-drc";
843 reg = <0x03440000 0x40000>;
848 clock-names = "ahb",
854 #address-cells = <1>;
855 #size-cells = <0>;
858 reg = <0>;
861 remote-endpoint = <&be1_out_drc1>;
866 reg = <1>;
869 remote-endpoint = <&tcon1_in_drc1>;
875 tcon0: lcd-controller@3c00000 {
876 compatible = "allwinner,sun9i-a80-tcon-lcd";
877 reg = <0x03c00000 0x10000>;
880 clock-names = "ahb", "tcon-ch0";
884 reset-names = "lcd",
887 clock-output-names = "tcon0-pixel-clock";
888 #clock-cells = <0>;
891 #address-cells = <1>;
892 #size-cells = <0>;
895 reg = <0>;
898 remote-endpoint = <&drc0_out_tcon0>;
903 reg = <1>;
908 tcon1: lcd-controller@3c10000 {
909 compatible = "allwinner,sun9i-a80-tcon-tv";
910 reg = <0x03c10000 0x10000>;
913 clock-names = "ahb", "tcon-ch1";
915 reset-names = "lcd", "edp";
918 #address-cells = <1>;
919 #size-cells = <0>;
922 reg = <0>;
925 remote-endpoint = <&drc1_out_tcon1>;
930 reg = <1>;
936 compatible = "allwinner,sun9i-a80-ccu";
937 reg = <0x06000000 0x800>;
939 clock-names = "hosc", "losc";
940 #clock-cells = <1>;
941 #reset-cells = <1>;
945 compatible = "allwinner,sun4i-a10-timer";
946 reg = <0x06000c00 0xa0>;
958 compatible = "allwinner,sun6i-a31-wdt";
959 reg = <0x06000ca0 0x20>;
965 compatible = "allwinner,sun9i-a80-pinctrl";
966 reg = <0x06000800 0x400>;
973 clock-names = "apb", "hosc", "losc";
974 gpio-controller;
975 interrupt-controller;
976 #interrupt-cells = <3>;
977 #gpio-cells = <3>;
979 gmac_rgmii_pins: gmac-rgmii-pins {
988 drive-strength = <40>;
991 i2c3_pins: i2c3-pins {
996 lcd0_rgb888_pins: lcd0-rgb888-pins {
1007 mmc0_pins: mmc0-pins {
1011 drive-strength = <30>;
1012 bias-pull-up;
1015 mmc1_pins: mmc1-pins {
1019 drive-strength = <30>;
1020 bias-pull-up;
1023 mmc2_8bit_pins: mmc2-8bit-pins {
1029 drive-strength = <30>;
1030 bias-pull-up;
1033 uart0_ph_pins: uart0-ph-pins {
1038 uart4_pins: uart4-pins {
1045 compatible = "snps,dw-apb-uart";
1046 reg = <0x07000000 0x400>;
1048 reg-shift = <2>;
1049 reg-io-width = <4>;
1056 compatible = "snps,dw-apb-uart";
1057 reg = <0x07000400 0x400>;
1059 reg-shift = <2>;
1060 reg-io-width = <4>;
1067 compatible = "snps,dw-apb-uart";
1068 reg = <0x07000800 0x400>;
1070 reg-shift = <2>;
1071 reg-io-width = <4>;
1078 compatible = "snps,dw-apb-uart";
1079 reg = <0x07000c00 0x400>;
1081 reg-shift = <2>;
1082 reg-io-width = <4>;
1089 compatible = "snps,dw-apb-uart";
1090 reg = <0x07001000 0x400>;
1092 reg-shift = <2>;
1093 reg-io-width = <4>;
1100 compatible = "snps,dw-apb-uart";
1101 reg = <0x07001400 0x400>;
1103 reg-shift = <2>;
1104 reg-io-width = <4>;
1111 compatible = "allwinner,sun6i-a31-i2c";
1112 reg = <0x07002800 0x400>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1122 compatible = "allwinner,sun6i-a31-i2c";
1123 reg = <0x07002c00 0x400>;
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1133 compatible = "allwinner,sun6i-a31-i2c";
1134 reg = <0x07003000 0x400>;
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1144 compatible = "allwinner,sun6i-a31-i2c";
1145 reg = <0x07003400 0x400>;
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1155 compatible = "allwinner,sun6i-a31-i2c";
1156 reg = <0x07003800 0x400>;
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1166 compatible = "allwinner,sun6i-a31-wdt";
1167 reg = <0x08001000 0x20>;
1173 compatible = "allwinner,sun9i-a80-prcm";
1174 reg = <0x08001400 0x200>;
1178 reg = <0x080014b0 0x4>;
1179 compatible = "allwinner,sun6i-a31-clock-reset";
1180 #reset-cells = <1>;
1183 nmi_intc: interrupt-controller@80015a0 {
1184 compatible = "allwinner,sun9i-a80-nmi";
1185 interrupt-controller;
1186 #interrupt-cells = <2>;
1187 reg = <0x080015a0 0xc>;
1192 compatible = "allwinner,sun6i-a31-ir";
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&r_ir_pins>;
1197 clock-names = "apb", "ir";
1199 reg = <0x08002000 0x40>;
1204 compatible = "snps,dw-apb-uart";
1205 reg = <0x08002800 0x400>;
1207 reg-shift = <2>;
1208 reg-io-width = <4>;
1215 compatible = "allwinner,sun9i-a80-r-pinctrl";
1216 reg = <0x08002c00 0x400>;
1220 clock-names = "apb", "hosc", "losc";
1221 gpio-controller;
1222 interrupt-controller;
1223 #interrupt-cells = <3>;
1224 #gpio-cells = <3>;
1226 r_ir_pins: r-ir-pins {
1231 r_rsb_pins: r-rsb-pins {
1234 drive-strength = <20>;
1235 bias-pull-up;
1240 compatible = "allwinner,sun8i-a23-rsb";
1241 reg = <0x08003400 0x400>;
1244 clock-frequency = <3000000>;
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&r_rsb_pins>;
1249 #address-cells = <1>;
1250 #size-cells = <0>;