Lines Matching +full:cortex +full:- +full:a15 +full:- +full:timer
1 # SPDX-License-Identifier: GPL-2.0
163 The ARM series is a line of low-power-consumption RISC chip designs
165 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
166 manufactured, but legacy ARM-based PC hardware remains popular in
177 supported in LLD until version 14. The combined range is -/+ 256 MiB,
270 Patch phys-to-virt and virt-to-phys translation functions at
274 This can only be used with non-XIP MMU kernels where the base
320 bool "MMU-based Paged Memory Management Support"
323 Select if you want MMU-based virtualised addressing space
358 # This is sorted alphabetically by mach-* pathname. However, plat-*
360 # plat- suffix) or along side the corresponding mach-* source.
362 source "arch/arm/mach-actions/Kconfig"
364 source "arch/arm/mach-alpine/Kconfig"
366 source "arch/arm/mach-artpec/Kconfig"
368 source "arch/arm/mach-aspeed/Kconfig"
370 source "arch/arm/mach-at91/Kconfig"
372 source "arch/arm/mach-axxia/Kconfig"
374 source "arch/arm/mach-bcm/Kconfig"
376 source "arch/arm/mach-berlin/Kconfig"
378 source "arch/arm/mach-clps711x/Kconfig"
380 source "arch/arm/mach-davinci/Kconfig"
382 source "arch/arm/mach-digicolor/Kconfig"
384 source "arch/arm/mach-dove/Kconfig"
386 source "arch/arm/mach-ep93xx/Kconfig"
388 source "arch/arm/mach-exynos/Kconfig"
390 source "arch/arm/mach-footbridge/Kconfig"
392 source "arch/arm/mach-gemini/Kconfig"
394 source "arch/arm/mach-highbank/Kconfig"
396 source "arch/arm/mach-hisi/Kconfig"
398 source "arch/arm/mach-hpe/Kconfig"
400 source "arch/arm/mach-imx/Kconfig"
402 source "arch/arm/mach-ixp4xx/Kconfig"
404 source "arch/arm/mach-keystone/Kconfig"
406 source "arch/arm/mach-lpc32xx/Kconfig"
408 source "arch/arm/mach-mediatek/Kconfig"
410 source "arch/arm/mach-meson/Kconfig"
412 source "arch/arm/mach-milbeaut/Kconfig"
414 source "arch/arm/mach-mmp/Kconfig"
416 source "arch/arm/mach-mstar/Kconfig"
418 source "arch/arm/mach-mv78xx0/Kconfig"
420 source "arch/arm/mach-mvebu/Kconfig"
422 source "arch/arm/mach-mxs/Kconfig"
424 source "arch/arm/mach-nomadik/Kconfig"
426 source "arch/arm/mach-npcm/Kconfig"
428 source "arch/arm/mach-omap1/Kconfig"
430 source "arch/arm/mach-omap2/Kconfig"
432 source "arch/arm/mach-orion5x/Kconfig"
434 source "arch/arm/mach-pxa/Kconfig"
436 source "arch/arm/mach-qcom/Kconfig"
438 source "arch/arm/mach-realtek/Kconfig"
440 source "arch/arm/mach-rpc/Kconfig"
442 source "arch/arm/mach-rockchip/Kconfig"
444 source "arch/arm/mach-s3c/Kconfig"
446 source "arch/arm/mach-s5pv210/Kconfig"
448 source "arch/arm/mach-sa1100/Kconfig"
450 source "arch/arm/mach-shmobile/Kconfig"
452 source "arch/arm/mach-socfpga/Kconfig"
454 source "arch/arm/mach-spear/Kconfig"
456 source "arch/arm/mach-sti/Kconfig"
458 source "arch/arm/mach-stm32/Kconfig"
460 source "arch/arm/mach-sunxi/Kconfig"
462 source "arch/arm/mach-tegra/Kconfig"
464 source "arch/arm/mach-ux500/Kconfig"
466 source "arch/arm/mach-versatile/Kconfig"
468 source "arch/arm/mach-vt8500/Kconfig"
470 source "arch/arm/mach-zynq/Kconfig"
472 # ARMv7-M architecture
481 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
490 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
491 with a range of available cores like Cortex-M3/M4/M7.
524 source "arch/arm/Kconfig-nommu"
542 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
545 Executing a SWP instruction to read-only memory does not set bit 11
563 This option enables the workaround for the 430973 Cortex-A8
566 same virtual address, whether due to self-modifying code or virtual
567 to physical address re-mapping, Cortex-A8 does not recover from the
568 stale interworking branch prediction. This results in Cortex-A8
573 available in non-secure mode.
580 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
587 register may not be available in non-secure mode and thus is not
596 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
600 workaround disables the write-allocate mode for the L2 cache via the
602 may not be available in non-secure mode and thus is not available on
611 This option enables the workaround for the 742230 Cortex-A9
615 the diagnostic register of the Cortex-A9 which causes the DMB
618 register may not be available in non-secure mode and thus is not
627 This option enables the workaround for the 742231 Cortex-A9
629 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
634 register of the Cortex-A9 which reduces the linefill issuing
636 diagnostics register may not be available in non-secure mode and thus
645 This option enables the workaround for the 643719 Cortex-A9 (prior to
655 This option enables the workaround for the 720789 Cortex-A9 (prior to
668 This option enables the workaround for the 743622 Cortex-A9
670 optimisation in the Cortex-A9 Store Buffer may lead to data
672 register of the Cortex-A9 which disables the Store Buffer
676 may not be available in non-secure mode and thus is not available on a
684 This option enables the workaround for the 751472 Cortex-A9 (prior
690 not be available in non-secure mode and thus is not available on
698 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
701 can populate the micro-TLB with a stale entry which may be hit with
709 This option enables the workaround for the 754327 Cortex-A9 (prior to
717 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
722 hit-under-miss enabled). It sets the undocumented bit 31 in
724 register, thus disabling hit-under-miss without putting the
733 affecting Cortex-A9 MPCore with two or more processors (all
746 This option enables the workaround for the 764319 Cortex-A9 erratum.
757 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
764 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
767 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
777 This option enables the workaround for the 773022 Cortex-A15
787 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
789 - Cortex-A12 852422: Execution of a sequence of instructions might
791 any Cortex-A12 cores yet.
800 This option enables the workaround for the 821420 Cortex-A12
804 deadlock when the VMOV instructions are issued out-of-order.
810 This option enables the workaround for the 825619 Cortex-A12
813 and Device/Strongly-Ordered loads and stores might cause deadlock
819 This option enables the workaround for the 857271 Cortex-A12
827 This option enables the workaround for the 852421 Cortex-A17
837 - Cortex-A17 852423: Execution of a sequence of instructions might
839 any Cortex-A17 cores yet.
840 This is identical to Cortex-A12 erratum 852422. It is a separate
848 This option enables the workaround for the 857272 Cortex-A17 erratum.
850 This is identical to Cortex-A12 erratum 857271. It is a separate
882 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
892 This option should be selected by machines which have an SMP-
895 The only effect of this option is to make the SMP-related
899 bool "Symmetric Multi-Processing"
909 If you say N here, the kernel will run on uni- and multiprocessor
915 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
916 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
917 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
926 SMP kernels contain instructions which fail on non-SMP processors.
953 bool "Multi-core scheduler support"
956 Multi-core scheduler support improves the CPU scheduler's decision
957 making when dealing with multi-core CPU chips at a cost of slightly
974 bool "Architected timer support"
978 This option enables support for the ARM architected timer
983 This options enables support for the ARM timer and watchdog unit
986 bool "Multi-Cluster Power Management"
990 for (multi-)cluster based systems, such as big.LITTLE based
1016 transparently handle transition between a cluster of A15's
1066 int "Maximum number of CPUs (2-32)"
1074 debugging is enabled, which uses half of the per-CPU fixmap
1078 bool "Support for hot-pluggable CPUs"
1091 implementing the PSCI specification for CPU-centric power
1103 prompt "Timer frequency"
1139 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1145 Thumb-2 mode.
1235 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1243 user-space 2nd level page tables to reside in high memory.
1246 bool "Enable privileged no-access"
1252 use-after-free bugs becoming an exploitable privilege escalation
1263 Enable use of CPU domains to implement privileged no-access.
1265 CPUs with low-vector mappings use a best-efforts implementation.
1273 Enable privileged no-access by disabling TTBR0 page table walks when
1295 Disabling this is usually safe for small single-platform
1319 address divisible by 4. On 32-bit ARM processors, these non-aligned
1322 correct operation of some network protocols. With an IP-only
1331 cores where a 8-word STM instruction give significantly higher
1338 However, if the CPU data cache is using a write-allocate mode,
1378 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1432 The physical address at which the ROM-able zImage is to be
1434 ROM-able zImage formats normally set this to a suitable
1444 for the ROM-able zImage which must be available while the
1447 Platforms which normally make use of ROM-able zImage formats
1500 Uses the command-line options passed by the boot loader instead of
1507 The command-line arguments provided by the boot loader will be
1518 architectures, you should supply some command-line options at build
1530 Uses the command-line options passed by the boot loader. If
1537 The command-line arguments provided by the boot loader will be
1546 command-line options your boot loader passes to the kernel.
1550 bool "Kernel Execute-In-Place from ROM"
1554 Execute-In-Place allows the kernel to run from non-volatile storage
1557 to RAM. Read-write sections, such as the data section and stack,
1614 will be determined at run-time, either by masking the current IP
1632 by UEFI firmware (such as non-volatile variables, realtime
1647 continue to boot on existing non-UEFI platforms.
1653 to be enabled much earlier than we do on ARM, which is non-trivial.
1676 your machine has an FPA or floating point co-processor podule.
1685 Say Y to include 80-bit support in the kernel floating-point
1686 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1687 Note that gcc does not generate 80-bit operations by default,
1700 It is very simple, and approximately 3-6 times faster than NWFPE.
1708 bool "VFP-format floating point maths"
1714 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for