trace/coresight/coresight-cpu-debug.rst

9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
15 debugger connects with SoC from JTAG port; on the other hand the program can
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
22 debug mechanism, Linux kernel can access these related registers from mmio
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32   registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
38   sampling registers: EDPCSR, EDVIDSR and EDCIDSR: from EDPCSR we can get
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52   If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53   but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54   instruction set state". For ARMv7-a, the driver checks furthermore if CPU
56   detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
59   If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
67 ----------------------
70 have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1
75                                 +---------------+
78                      +----------+--+            |
79         dbg_clock -->|          |**|            |<-- cpu_clock
81  dbg_power_domain -->|          |**|            |<-- cpu_power_domain
82                      +----------+--+            |
85                                 +---------------+
87 For debug domain, the user uses DT binding "clocks" and "power-domains" to
93 schemes and finally this heavily impacts external debug module. So we can
96 - On systems with a sane power controller which can behave correctly with
97   respect to CPU power domain, the CPU power domain can be controlled by
100   of CPU power down. As result, this can ensure the CPU power domain is
103 - Some designs will power down an entire cluster if all CPUs on the cluster
104   are powered down - including the parts of the debug registers that should
118 --------------------
120 See Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml for
125 ---------------------
127 If you want to enable debugging functionality at boot time, you can add
130 The driver also can work as module, so can enable the debugging when insmod
136 uses the debugfs file system to provide a knob to dynamically enable or disable
143 To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable::
150 firstly constraint CPU idle states before enable CPU debugging feature; so can
153 If you want to limit idle states at boot time, you can use "nohlt" or
156 At the runtime you can disable idle states with below methods:
158 It is possible to disable CPU idle states by way of the PM QoS
169   # exec 3<>-
171 The same can also be done from an application program.
173 Disable specific CPU's specific idle state from cpuidle sysfs (see
174 Documentation/admin-guide/pm/cpuidle.rst)::
176   # echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable
179 -------------
184   coresight-cpu-debug 850000.debug: CPU[0]:
185   coresight-cpu-debug 850000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
186   coresight-cpu-debug 850000.debug:  EDPCSR:  handle_IPI+0x174/0x1d8
187   coresight-cpu-debug 850000.debug:  EDCIDSR: 00000000
188 …coresight-cpu-debug 850000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…
189   coresight-cpu-debug 852000.debug: CPU[1]:
190   coresight-cpu-debug 852000.debug:  EDPRSR:  00000001 (Power:On DLK:Unlock)
191   coresight-cpu-debug 852000.debug:  EDPCSR:  debug_notifier_call+0x23c/0x358
192   coresight-cpu-debug 852000.debug:  EDCIDSR: 00000000
193 …coresight-cpu-debug 852000.debug:  EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMI…