Documentation/iio/ad4030.rst

1 .. SPDX-License-Identifier: GPL-2.0-only
16 * `AD4030-24 <https://www.analog.com/AD4030-24>`_
17 * `AD4032-24 <https://www.analog.com/AD4032-24>`_
18 * `AD4630-16 <https://www.analog.com/AD4630-16>`_
19 * `AD4630-24 <https://www.analog.com/AD4630-24>`_
20 * `AD4632-16 <https://www.analog.com/AD4632-16>`_
21 * `AD4632-24 <https://www.analog.com/AD4632-24>`_
29 - One channel for the differential data
30 - One channel for the common byte.
34 +------------------------------------+------------------------------------+
37 | - voltage0-voltage1 (differential) | - voltage0-voltage1 (differential) |
38 | - voltage2 (common-mode)           | - voltage2-voltage3 (differential) |
39 |                                    | - voltage4 (common-mode)           |
40 |                                    | - voltage5 (common-mode)           |
41 +------------------------------------+------------------------------------+
44 ------
48 common-mode channel, the label is ``common-modeN`` where ``N`` is the
53 +-----------------+-----------------+
56 | - differential0 | - differential0 |
57 | - common-mode0  | - differential1 |
58 |                 | - common-mode0  |
59 |                 | - common-mode1  |
60 +-----------------+-----------------+
66 ----------------
70 One lane mode
73 In this mode, each channel has its own SDO line to send the conversion results.
74 At the moment this mode can only be used on AD4030 which has one channel so only
77 .. code-block::
79     +-------------+         +-------------+
82     |         CNV |<--------| CNV         |
83     |          CS |<--------| CS          |
84     |         SDI |<--------| SDO         |
85     |        SDO0 |-------->| SDI         |
86     |        SCLK |<--------| SCLK        |
87     +-------------+         +-------------+
89 Interleaved mode
92 In this mode, both channels conversion results are bit interleaved one SDO line.
93 As such the wiring is the same as `One lane mode`_.
95 SPI Clock mode
96 --------------
98 Only the SPI clocking mode is supported.
101 ------------
104 datasheet. This is due to the `Differential data + common-mode`_ encoding
112 This mode is selected when:
114 - Only differential channels are enabled in a buffered read
115 - Oversampling attribute is set to 1
117 Differential data + common-mode
120 This mode is selected when:
122 - Differential and common-mode channels are enabled in a buffered read
123 - Oversampling attribute is set to 1
125 For the 24-bits chips, this mode is also available with 16-bits differential
131 This mode is selected when:
133 - Only differential channels are selected enabled in a buffered read
134 - Oversampling attribute is greater than 1
137 -----------------------
139 Each differential data channel has a 16-bits unsigned configurable hardware
144 For the ADCs ending in ``-24``, the gain is encoded on 24-bits.
145 Likewise, the ADCs ending in ``-16`` have a gain encoded on 16-bits. Note that
155 -----------------
159 at the device tree to determine which is being used. If ``ref-supply`` is
161 disabled. If ``refin-supply`` is present, then the internal buffered reference
165 -----
168 device tree to see if the ``reset-gpio`` is populated.
173 ----------------------
175 - ``BUSY`` indication
176 - Additional wiring modes
177 - Additional clock modes
178 - Differential data 16-bits + common-mode for 24-bits chips
179 - Overrange events
180 - Test patterns