amdgpu/display/programming-model-dcn.rst

5 In the :ref:`Display Core Next (DCN) <dcn_overview>` and :ref:`DCN Block
7 interact with each other. On this page, the focus is shifted to the display
11 configuration. See DC as a service available for a Display Manager (amdgpu_dm)
21 From the display hardware perspective, it is plausible to expect that if a
22 problem is well-defined, it will probably be implemented at the hardware level.
24 a very well-defined scope, the solution is usually implemented as a policy at
44 Unfortunately, there is no straight-forward analytic way to determine if a
46 variables related to this problem (e.g., many different DCN/DCE hardware
50 create and maintain, and amdgpu driver relies on Display Mode Library (DML) to
55 give the reader some idea about the complexity of driving a display from the
57 over the amdgpu display code.
59 Display Driver Architecture Overview
62 The diagram below provides an overview of the display driver architecture;
65 .. kernel-figure:: dc-components.svg
67 The first layer of the diagram is the high-level DC API represented by the
72 API (`dc/inc/hw`), which represents each DCN low-level block, such as HUBP,
78 -------------
80 The below diagram outlines the basic display objects. In particular, pay
84 .. kernel-figure:: dc-arch-overview.svg
92 is a low-level abstraction for the connector. One interesting aspect of the
94 platform/board and not by the SoC. The `dc_link` struct is the high-level data
97 represents the connected display.
106 elaborated in the DCN overview page  (check the DCN block diagram :ref:`Display
110 represents the data flow from the connector to the display. Next we have
113 version of `drm_crtc` and represents the post-blending pipeline.
117 pre-blending portion of the pipeline. This image was probably processed by GFX
123 ----------------
137 for the hardware-specific initialization, whereas `dc_hardware_init` does the
145 the display by using the `dc_link_detect()` function. After the driver figures
146 out if any display is connected to the device, the challenging phase starts:
148 configuration is not a DC task since this is the Display Manager (`amdgpu_dm`)
153 important to add that even if the display supports some specific configuration,
158 the best-case scenario, you might be able to turn the display on with a black