driver-api/soundwire/bra.rst

6 -----------
12 ------------
14 The SoundWire 1.x specification provides a mechanism to speed-up
20 one byte per frame with write/read commands. With a typical 48kHz
28       10-byte overhead per frame (header and footer response).
35   (3) The targeted Peripheral device SHALL support the optional Data
36       Port 0, and likewise the Manager SHALL expose audio-like Ports
41       bandwidth. If there are no on-going audio transfers, the entire
48   (5) The number of bits transferred per frame SHALL be a multiple of
61       need to be spaced in time or flow-controlled.
67       peripheral to deal with the previous transfer. In addition BRA
70   (9) Up to 470 bytes may be transmitted per frame.
78 --------------
84   (1) A CRC on the 7-byte header. This CRC helps the Peripheral Device
86       bytes. The Peripheral Device provides a response in Byte 7.
89       transmitted as the last-but-one byte in the packet, prior to the
104 -------------
112 	+---+--------------------------------------------+
116 	+   +--------------------------------------------+
118 	+ O +--------------------------------------------+
120 	+ M +--------------------------------------------+
127 	+   +--------------------------------------------+
129 	+   +--------------------------------------------+
131 	+---+--------------------------------------------+
137     - HSTART = 1
138     - HSTOP = N - 1
139     - Sampling Interval = N
140     - WordLength = N - 1
143 -----------------------
150 this would only be beneficial for single-link solutions.
152 In the case of multiple Peripheral devices attached to different
155 streams, possibly in parallel - the links are really independent.
158 --------------------
163   (1) Transfers initiated by a Peripheral Device. The BRA Initiator is
166   (2) Flow-control capabilities and retransmission based on the
170 Bi-directional handling
171 -----------------------
174 packet the header and footer response are provided by the Peripheral
175 Target device. On the Peripheral device, the BRA protocol is handled
176 by a single DP0 data port, and at the low-level the bus ownership can
180 On the host side, most implementations rely on a Port-like concept,
182 (Host->Peripheral and Peripheral->Host). The amount of data
197 retry a transfer in case of errors. However, as for the flow-control
206 Manager level, so the low-level BPT/BRA details must be hidden in
207 Manager-specific code. For example the Cadence IP format above is not
212 Manager-specific code.
215 DMA, or other host-DSP communication protocols. The codec driver
227 mutex for regular read/write and BRA is a show-stopper. Independent
234 In addition, the 'sdw_msg' structure hard-codes support for 16-bit
236 support based on native 32-bit addresses. A separate API with
239 One possible strategy to speed-up all initialization tasks would be to
248 Peripheral/bus interface
249 ------------------------
253     - sdw_bpt_send_async(bpt_message)
256       implementation-defined capabilities (typically DMA or IPC
262    - sdw_bpt_wait()
274 send/wait API suggested above, so at a high-level it would seem
276 is available or not, and use a regular read-write command channel in
282 ----------------
293        can be programmed blindly without knowing what Peripheral is
297        COMMAND_IGNORED responses that will be wired-ORed with
310    (4) With the assumption that a single BRA stream is used per link,
311        that stream can connect master ports as well as all peripheral
316        concept of multi-link aggregation allowed by regular DAI links.
319 -----------------
328 transfer. The format is based on 192kHz 32-bit samples, and the number
335 but at the platform-level, e.g. for Intel the data sizes must be