Lines Matching +full:isa +full:- +full:extensions
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
17 are "vendor" extensions.
23 The properties for standard extensions therefore map to their originally
24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.
34 riscv,isa:
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from
41 Due to revisions of the ISA specification, some deviations
43 Notably, riscv,isa was defined prior to the creation of the
44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
47 While the isa strings in ISA specification are case
48 insensitive, letters in the riscv,isa string must be all
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
54 riscv,isa-base:
56 The base ISA implemented by this hart, as described by the 20191213
57 version of the unprivileged ISA specification.
59 - rv32i
60 - rv64i
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/string-array
65 description: Extensions supported by the hart.
68 # single letter extensions, in canonical order
69 - const: i
72 version of the unprivileged ISA specification.
75 the Zicntr and Zihpm extensions after the ratification of the
78 - const: m
81 ratified in the 20191213 version of the unprivileged ISA
84 - const: a
87 20191213 version of the unprivileged ISA specification.
89 - const: f
91 The standard F extension for single-precision floating point, as
92 ratified in the 20191213 version of the unprivileged ISA
95 - const: d
97 The standard D extension for double-precision floating-point, as
98 ratified in the 20191213 version of the unprivileged ISA
101 - const: q
103 The standard Q extension for quad-precision floating-point, as
104 ratified in the 20191213 version of the unprivileged ISA
107 - const: c
110 the 20191213 version of the unprivileged ISA specification.
112 - const: v
115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec.
118 - const: h
121 version of the privileged ISA specification.
123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia
126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine-mode-visible csr and behavioural
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
131 - const: smmpm
133 The standard Smmpm extension for M-mode pointer masking as
135 of riscv-j-extension.
137 - const: smnpm
139 The standard Smnpm extension for next-mode pointer masking as
141 of riscv-j-extension.
143 - const: smstateen
146 added by other RISC-V extensions in H/S/VS/U/VU modes and as
147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
149 - const: ssaia
151 The standard Ssaia supervisor-level extension for the advanced
152 interrupt architecture for supervisor-mode-visible csr and
154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
156 - const: sscofpmf
158 The standard Sscofpmf supervisor-level extension for count overflow
159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
160 to manually trigger workflow. (#2)") of riscv-count-overflow.
162 - const: ssnpm
164 The standard Ssnpm extension for next-mode pointer masking as
166 of riscv-j-extension.
168 - const: sstc
170 The standard Sstc supervisor-level extension for time compare as
172 workflow. (#2)") of riscv-time-compare.
174 - const: svade
176 The standard Svade supervisor-level extension for SW-managed PTE A/D
178 ISA specification.
180 Both Svade and Svadu extensions control the hardware behavior when
182 possible combinations of these extensions in the device tree are:
192 Svadu turned-off at boot time. To use Svadu, supervisor must
195 - const: svadu
197 The standard Svadu supervisor-level extension for hardware updating
199 privileged ISA specification. Please refer to Svade dt-binding
202 - const: svinval
204 The standard Svinval supervisor-level extension for fine-grained
205 address-translation cache invalidation as ratified in the 20191213
206 version of the privileged ISA specification.
208 - const: svnapot
210 The standard Svnapot supervisor-level extensions for napot
212 privileged ISA specification.
214 - const: svpbmt
216 The standard Svpbmt supervisor-level extensions for page-based
218 ISA specification.
220 - const: svvptc
222 The standard Svvptc supervisor-level extension for
223 address-translation cache behaviour with respect to invalid entries
225 riscv-svvptc.
227 - const: zaamo
231 (#1304)") of the unprivileged ISA specification.
233 - const: zabha
237 riscv-zabha.
239 - const: zacas
241 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
243 ratified") of the riscv-zacas.
245 - const: zalrsc
247 The standard Zalrsc extension for load-reserved/store-conditional as
249 (#1304)") of the unprivileged ISA specification.
251 - const: zawrs
253 The Zawrs extension for entering a low-power state or for trapping
256 riscv/zawrs") of riscv-isa-manual.
258 - const: zba
260 The standard Zba bit-manipulation extension for address generation
262 request #158 from hirooih/clmul-fix-loop-end-condition") of
263 riscv-bitmanip.
265 - const: zbb
267 The standard Zbb bit-manipulation extension for basic bit-manipulation
269 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
271 - const: zbc
273 The standard Zbc bit-manipulation extension for carry-less
275 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
277 - const: zbkb
280 in version 1.0 of RISC-V Cryptography Extensions Volume I
283 - const: zbkc
285 The standard Zbkc carry-less multiply instructions as ratified
286 in version 1.0 of RISC-V Cryptography Extensions Volume I
289 - const: zbkx
292 in version 1.0 of RISC-V Cryptography Extensions Volume I
295 - const: zbs
297 The standard Zbs bit-manipulation extension for single-bit
299 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
301 - const: zca
303 The Zca extension part of Zc* standard extensions for code size
305 RV64 as it contains no instructions") of riscv-code-size-reduction,
306 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
309 - const: zcb
311 The Zcb extension part of Zc* standard extensions for code size
313 RV64 as it contains no instructions") of riscv-code-size-reduction,
314 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
317 - const: zcd
319 The Zcd extension part of Zc* standard extensions for code size
321 RV64 as it contains no instructions") of riscv-code-size-reduction,
322 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
325 - const: zcf
327 The Zcf extension part of Zc* standard extensions for code size
329 RV64 as it contains no instructions") of riscv-code-size-reduction,
330 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
333 - const: zcmop
336 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
338 - const: zfa
342 riscv-isa-manual.
344 - const: zfbfmin
347 16-bit half-precision brain floating-point instructions, as ratified
348 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
350 - const: zfh
352 The standard Zfh extension for 16-bit half-precision binary
353 floating-point instructions, as ratified in commit 64074bc ("Update
354 version numbers for Zfh/Zfinx") of riscv-isa-manual.
356 - const: zfhmin
359 16-bit half-precision binary floating-point instructions, as ratified
361 riscv-isa-manual.
363 - const: ziccrse
369 - const: zk
372 in version 1.0 of RISC-V Cryptography Extensions Volume I
375 - const: zkn
377 The standard Zkn NIST algorithm suite extensions as ratified in
378 version 1.0 of RISC-V Cryptography Extensions Volume I
381 - const: zknd
384 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
387 - const: zkne
390 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
393 - const: zknh
396 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
399 - const: zkr
402 1.0 of RISC-V Cryptography Extensions Volume I specification.
405 device-tree has been provided.
407 - const: zks
409 The standard Zks ShangMi algorithm suite extensions as ratified in
410 version 1.0 of RISC-V Cryptography Extensions Volume I
413 - const: zksed
416 as ratified in version 1.0 of RISC-V Cryptography Extensions
419 - const: zksh
422 as ratified in version 1.0 of RISC-V Cryptography Extensions
425 - const: zkt
428 in version 1.0 of RISC-V Cryptography Extensions Volume I
431 - const: zicbom
434 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
436 - const: zicbop
438 The standard Zicbop extension for cache-block prefetch instructions
439 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
440 riscv-CMOs.
442 - const: zicboz
444 The standard Zicboz extension for cache-block zeroing as ratified
445 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
447 - const: zicntr
450 ratified in the 20191213 version of the unprivileged ISA
453 - const: zicond
456 conditional-select/move operations as ratified in commit 95cf1f9
457 ("Add changes requested by Ved during signoff") of riscv-zicond.
459 - const: zicsr
463 unprivileged ISA specification.
466 special case read-only CSRs, that were moved into the Zicntr and
467 Zihpm extensions after the ratification of the 20191213 version of
470 - const: zifencei
472 The standard Zifencei extension for instruction-fetch fence, as
473 ratified in the 20191213 version of the unprivileged ISA
476 - const: zihintpause
479 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
481 - const: zihintntl
483 The standard Zihintntl extension for non-temporal locality hints, as
485 riscv-isa-manual.
487 - const: zihpm
490 ratified in the 20191213 version of the unprivileged ISA
493 - const: zimop
496 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
498 - const: ztso
502 riscv-isa-manual.
504 - const: zvbb
506 The standard Zvbb extension for vectored basic bit-manipulation
508 riscv-crypto-spec-vector.adoc") of riscv-crypto.
510 - const: zvbc
514 riscv-crypto-spec-vector.adoc") of riscv-crypto.
516 - const: zve32f
519 in commit 6f702a2 ("Vector extensions are now ratified") of
520 riscv-v-spec.
522 - const: zve32x
525 in commit 6f702a2 ("Vector extensions are now ratified") of
526 riscv-v-spec.
528 - const: zve64d
531 in commit 6f702a2 ("Vector extensions are now ratified") of
532 riscv-v-spec.
534 - const: zve64f
537 in commit 6f702a2 ("Vector extensions are now ratified") of
538 riscv-v-spec.
540 - const: zve64x
543 in commit 6f702a2 ("Vector extensions are now ratified") of
544 riscv-v-spec.
546 - const: zvfbfmin
549 16-bit half-precision brain floating-point instructions, as ratified
550 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
552 - const: zvfbfwma
554 The standard Zvfbfwma extension for vectored half-precision brain
555 floating-point widening multiply-accumulate instructions, as ratified
556 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual.
558 - const: zvfh
560 The standard Zvfh extension for vectored half-precision
561 floating-point instructions, as ratified in commit e2ccd05
562 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
564 - const: zvfhmin
566 The standard Zvfhmin extension for vectored minimal half-precision
567 floating-point instructions, as ratified in commit e2ccd05
568 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
570 - const: zvkb
572 The standard Zvkb extension for vector cryptography bit-manipulation
574 riscv-crypto-spec-vector.adoc") of riscv-crypto.
576 - const: zvkg
579 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
580 of riscv-crypto.
582 - const: zvkn
585 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
586 of riscv-crypto.
588 - const: zvknc
592 riscv-crypto-spec-vector.adoc") of riscv-crypto.
594 - const: zvkned
598 riscv-crypto-spec-vector.adoc") of riscv-crypto.
600 - const: zvkng
604 riscv-crypto-spec-vector.adoc") of riscv-crypto.
606 - const: zvknha
608 The standard Zvknha extension for NIST suite: vector SHA-2 secure,
609 hash (SHA-256 only) instructions, as ratified in commit
610 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
612 - const: zvknhb
614 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
615 hash (SHA-256 and SHA-512) instructions, as ratified in commit
616 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
618 - const: zvks
622 riscv-crypto-spec-vector.adoc") of riscv-crypto.
624 - const: zvksc
628 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
630 - const: zvksed
634 riscv-crypto-spec-vector.adoc") of riscv-crypto.
636 - const: zvksh
640 riscv-crypto-spec-vector.adoc") of riscv-crypto.
642 - const: zvksg
646 riscv-crypto-spec-vector.adoc") of riscv-crypto.
648 - const: zvkt
650 The standard Zvkt extension for vector data-independent execution
652 riscv-crypto-spec-vector.adoc") of riscv-crypto.
654 # vendor extensions, each extension sorted alphanumerically under the
658 - const: xandespmu
663 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
665 # T-HEAD
666 - const: xtheadvector
668 The T-HEAD specific 0.7.1 vector implementation as written in
669 …https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/…
672 - if:
679 - if:
686 - if:
691 - contains:
693 - contains:
696 - if:
701 - contains:
703 - contains:
706 - if:
713 - if:
720 - if:
725 - contains:
727 - contains:
730 - if:
735 - contains:
737 - contains:
740 - if:
747 - if:
754 - if:
759 - contains:
761 - contains:
764 - if:
771 - if:
776 - contains:
778 - contains:
780 - contains:
783 - if:
788 - contains:
790 - contains:
793 - if:
796 - const: zvbc
797 - const: zvkn
798 - const: zvknc
799 - const: zvkng
800 - const: zvknhb
801 - const: zvksc
805 - const: v
806 - const: zve64x
808 - if:
811 - const: zvbb
812 - const: zvkb
813 - const: zvkg
814 - const: zvkned
815 - const: zvknha
816 - const: zvksed
817 - const: zvksh
818 - const: zvks
819 - const: zvkt
823 - const: v
824 - const: zve32x
828 - if:
830 riscv,isa-extensions:
833 riscv,isa-base:
838 riscv,isa-extensions: