bindings/pci/xilinx-versal-cpm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
13   - $ref: /schemas/pci/pci-host-bridge.yaml#
18       - xlnx,versal-cpm-host-1.00
19       - xlnx,versal-cpm5-host
20       - xlnx,versal-cpm5-host1
21       - xlnx,versal-cpm5nc-host
25       - description: CPM system level control and status registers.
26       - description: Configuration space region and bridge registers.
27       - description: CPM5 control and status registers.
30   reg-names:
32       - const: cpm_slcr
33       - const: cfg
34       - const: cpm_csr
40   msi-map:
47   "#interrupt-cells":
50   interrupt-controller:
51     description: Interrupt controller node for handling legacy PCI interrupts.
56       "#address-cells":
59       "#interrupt-cells":
62       interrupt-controller: true
65   - reg
66   - reg-names
67   - "#interrupt-cells"
68   - interrupts
69   - interrupt-map
70   - interrupt-map-mask
71   - bus-range
72   - msi-map
73   - interrupt-controller
78   - |
81                #address-cells = <2>;
82                #size-cells = <2>;
84                        compatible = "xlnx,versal-cpm-host-1.00";
86                        #address-cells = <3>;
87                        #interrupt-cells = <1>;
88                        #size-cells = <2>;
90                        interrupt-parent = <&gic>;
91                        interrupt-map-mask = <0 0 0 7>;
92                        interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
96                        bus-range = <0x00 0xff>;
99                        msi-map = <0x0 &its_gic 0x0 0x10000>;
102                        reg-names = "cpm_slcr", "cfg";
103                        pcie_intc_0: interrupt-controller {
104                                #address-cells = <0>;
105                                #interrupt-cells = <1>;
106                                interrupt-controller;
111                        compatible = "xlnx,versal-cpm5-host";
113                        #address-cells = <3>;
114                        #interrupt-cells = <1>;
115                        #size-cells = <2>;
117                        interrupt-parent = <&gic>;
118                        interrupt-map-mask = <0 0 0 7>;
119                        interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
123                        bus-range = <0x00 0xff>;
126                        msi-map = <0x0 &its_gic 0x0 0x10000>;
130                        reg-names = "cpm_slcr", "cfg", "cpm_csr";
132                        pcie_intc_1: interrupt-controller {
133                                #address-cells = <0>;
134                                #interrupt-cells = <1>;
135                                interrupt-controller;