Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
13 - $ref: /schemas/pci/pci-host-bridge.yaml#
14 - $ref: /schemas/pci/snps,dw-pcie.yaml#
18 const: amd,versal2-mdb-host
22 - description: MDB System Level Control and Status Register (SLCR) Base
23 - description: configuration region
24 - description: data bus interface
25 - description: address translation unit register
27 reg-names:
29 - const: slcr
30 - const: config
31 - const: dbi
32 - const: atu
37 msi-map:
43 interrupt-map-mask:
45 - const: 0
46 - const: 0
47 - const: 0
48 - const: 7
50 interrupt-map:
53 "#interrupt-cells":
56 interrupt-controller:
57 description: identifies the node as an interrupt controller
61 interrupt-controller: true
63 "#address-cells":
66 "#interrupt-cells":
70 - interrupt-controller
71 - "#address-cells"
72 - "#interrupt-cells"
75 - reg
76 - reg-names
77 - interrupts
78 - interrupt-map
79 - interrupt-map-mask
80 - msi-map
81 - "#interrupt-cells"
82 - interrupt-controller
87 - |
88 #include <dt-bindings/interrupt-controller/arm-gic.h>
89 #include <dt-bindings/interrupt-controller/irq.h>
92 #address-cells = <2>;
93 #size-cells = <2>;
95 compatible = "amd,versal2-mdb-host";
100 reg-names = "slcr", "config", "dbi", "atu";
104 interrupt-parent = <&gic>;
105 interrupt-map-mask = <0 0 0 7>;
106 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
110 msi-map = <0x0 &gic_its 0x00 0x10000>;
111 #address-cells = <3>;
112 #size-cells = <2>;
113 #interrupt-cells = <1>;
115 pcie_intc_0: interrupt-controller {
116 #address-cells = <0>;
117 #interrupt-cells = <1>;
118 interrupt-controller;