bindings/pci/altr%2Cpcie-root-port.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11   - Matthew Gerlach <matthew.gerlach@linux.intel.com>
16       PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
18       altr,pcie-root-port-2.0. The Agilex family of chips has three,
19       non-register compatible, variants of PCIe Hard IP referred to as the
20       F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
23       - altr,pcie-root-port-1.0
24       - altr,pcie-root-port-2.0
25       - altr,pcie-root-port-3.0-f-tile
26       - altr,pcie-root-port-3.0-p-tile
27       - altr,pcie-root-port-3.0-r-tile
31       - description: TX slave port region
32       - description: Control register access region
33       - description: Hard IP region
36   reg-names:
38       - const: Txs
39       - const: Cra
40       - const: Hip
46   interrupt-controller: true
48   interrupt-map-mask:
50       - const: 0
51       - const: 0
52       - const: 0
53       - const: 7
55   interrupt-map:
58   "#interrupt-cells":
61   msi-parent: true
64   - compatible
65   - reg
66   - reg-names
67   - interrupts
68   - "#interrupt-cells"
69   - interrupt-controller
70   - interrupt-map
71   - interrupt-map-mask
74   - $ref: /schemas/pci/pci-host-bridge.yaml#
75   - if:
79             - altr,pcie-root-port-1.0
85         reg-names:
93         reg-names:
100   - |
101     #include <dt-bindings/interrupt-controller/arm-gic.h>
102     #include <dt-bindings/interrupt-controller/irq.h>
104         compatible = "altr,pcie-root-port-1.0";
107         reg-names = "Txs", "Cra";
108         interrupt-parent = <&hps_0_arm_gic_0>;
110         interrupt-controller;
111         #interrupt-cells = <1>;
112         bus-range = <0x0 0xff>;
114         msi-parent = <&msi_to_gic_gen_0>;
115         #address-cells = <3>;
116         #size-cells = <2>;
117         interrupt-map-mask = <0 0 0 7>;
118         interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>,