bindings/net/ethernet-controller.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - David S. Miller <davem@davemloft.net>
19   local-mac-address:
22     $ref: /schemas/types.yaml#/definitions/uint8-array
26   mac-address:
31       local-mac-address property.
32     $ref: /schemas/types.yaml#/definitions/uint8-array
36   max-frame-size:
43   max-speed:
48   nvmem-cells:
53   nvmem-cell-names:
54     const: mac-address
56   phy-connection-type:
64       - internal
65       - mii
66       - gmii
67       - sgmii
68       - psgmii
69       - qsgmii
70       - qusgmii
71       - tbi
72       - rev-mii
73       - rmii
74       - rev-rmii
75       - moca
77       # RX and TX delays are provided by the PCB. See below
78       - rgmii
80       # RX and TX delays are not provided by the PCB. This is the most
82       - rgmii-id
84       # TX delay is provided by the PCB. See below
85       - rgmii-rxid
87       # RX delay is provided by the PCB. See below
88       - rgmii-txid
89       - rtbi
90       - smii
91       - xgmii
92       - trgmii
93       - 1000base-x
94       - 2500base-x
95       - 5gbase-r
96       - rxaui
97       - xaui
99       # 10GBASE-KR, XFI, SFI
100       - 10gbase-kr
101       - usxgmii
102       - 10gbase-r
103       - 25gbase-r
104       - 10g-qxgmii
106   phy-mode:
107     $ref: "#/properties/phy-connection-type"
109   pcs-handle:
110     $ref: /schemas/types.yaml#/definitions/phandle-array
115       bus to link with an external PHY (phy-handle) if exists.
117   pcs-handle-names:
119       The name of each PCS in pcs-handle.
121   phy-handle:
127     $ref: "#/properties/phy-handle"
130   phy-device:
131     $ref: "#/properties/phy-handle"
134   rx-fifo-depth:
147   tx-fifo-depth:
155       Specifies the PHY management type. If auto is set and fixed-link
160       - auto
161       - in-band-status
163   fixed-link:
165       - $ref: /schemas/types.yaml#/definitions/uint32-array
168           - minimum: 0
172               specified fixed-links
174           - enum: [0, 1]
179           - enum: [10, 100, 1000, 2500, 10000]
183           - enum: [0, 1]
187           - enum: [0, 1]
191       - type: object
200           full-duplex:
203               Indicates that full-duplex is used. When absent, half
211           asym-pause:
216           link-gpios:
222           - speed
234       '#address-cells':
237       '#size-cells':
241       '^led@[a-f0-9]+$':
253           - reg
260   pcs-handle-names: [pcs-handle]
263   - if:
265         phy-mode:
268               - rgmii
269               - rgmii-rxid
270               - rgmii-txid
271               - rgmii-id
274         rx-internal-delay-ps:
276             RGMII Receive Clock Delay defined in pico seconds. This is used for
277             controllers that have configurable RX internal delays. If this
278             property is present then the MAC applies the RX delay.
279         tx-internal-delay-ps:
281             RGMII Transmit Clock Delay defined in pico seconds. This is used for
282             controllers that have configurable TX internal delays. If this
283             property is present then the MAC applies the TX delay.
290 # 'phy-modes' & 'phy-connection-type' properties 'rgmii', 'rgmii-id',
291 # 'rgmii-rxid', and 'rgmii-txid' are frequently used wrongly by
294 # The RGMII specification requires a 2ns delay between the data and
295 # clock signals on the RGMII bus. How this delay is implemented is not
300 # delay. If both the RX and TX delays are implemented in this manner,
304 # 'rgmii-id' should be used. Here, 'id' refers to 'internal delay',
305 # where either the MAC or PHY adds the delay.
308 # lines, either 'rgmii-rxid' or 'rgmii-txid' should be used,
310 # internally, while the PCB implements the other delay.
317 # any RGMII phy mode other than 'rgmii-id' is probably wrong, and is
334 # to read the 'phy-mode' from Device Tree, not implement any delays,
336 # specified by the 'phy-mode'. The PHY should always be reconfigured
347 # delays which cannot be disabled. The 'phy-mode' only describes the
349 # the meaning of 'phy-mode'. It does however mean that a 'phy-mode' of
353 # cannot be supported. When the MAC implements the delay, it must
354 # ensure that the PHY does not also implement the same delay. So it
355 # must modify the phy-mode it passes to the PHY, removing the delay it
356 # has added. Failure to remove the delay will result in a
357 # non-functioning link.
361 # properties 'rx-internal-delay-ps' and 'tx-internal-delay-ps' should
363 # expected here are small. A value of 2000ps, i.e 2ns, and a phy-mode
367 # 'rx-internal-delay-ps' and 'tx-internal-delay-ps' in the PHY node
368 # should be used. When the PHY is implementing delays, e.g. 'rgmii-id'
369 # these properties should have a value near to 2000ps. If the PCB is
371 # tune the delay added by the PCB.