Lines Matching +full:2 +full:rgmii

78       - rgmii
82       - rgmii-id
85       - rgmii-rxid
88       - rgmii-txid
268               - rgmii
269               - rgmii-rxid
270               - rgmii-txid
271               - rgmii-id
276             RGMII Receive Clock Delay defined in pico seconds. This is used for
281             RGMII Transmit Clock Delay defined in pico seconds. This is used for
290 # 'phy-modes' & 'phy-connection-type' properties 'rgmii', 'rgmii-id',
291 # 'rgmii-rxid', and 'rgmii-txid' are frequently used wrongly by
294 # The RGMII specification requires a 2ns delay between the data and
295 # clock signals on the RGMII bus. How this delay is implemented is not
299 # data traces. A sufficiently difference in length can provide the 2ns
301 # 'rgmii' should be used, so indicating the PCB adds the delays.
304 # 'rgmii-id' should be used. Here, 'id' refers to 'internal delay',
308 # lines, either 'rgmii-rxid' or 'rgmii-txid' should be used,
317 # any RGMII phy mode other than 'rgmii-id' is probably wrong, and is
340 # Experience to date is that all PHYs which implement RGMII also
350 # 'rgmii' is now invalid, it cannot be supported, since both the PCB
363 # expected here are small. A value of 2000ps, i.e 2ns, and a phy-mode
364 # of 'rgmii' will not be accepted by Reviewers.
368 # should be used. When the PHY is implementing delays, e.g. 'rgmii-id'
370 # implementing delays, e.g. 'rgmii', a small value can be used to fine