Lines Matching +full:mtk +full:- +full:vcodec +full:- +full:lat
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yunfei Dong <yunfei.dong@mediatek.com>
14 MediaTek SoCs that supports high-resolution decoding functionalities.
19 +------------------------------------------------+------------------------------+
21 | input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer |
23 +--------------||-----------||-------------------+-------||---------------------+
24 LAT Workqueue | Core Workqueue <parent>
25 ---------------||-----------||-------------------|-------||----------------------
26 ||<----------||---------HW index--------->|| <child>
28 +-------------------------------------------------------------+
31 | (lat/lat-soc/core0/core1) |
32 +-------------------------------------------------------------+
35 pipeline, such as LAT-SoC, LAT and Core.
45 1. LAT Workqueue, for LAT-SoC and LAT decoder:
46 Its workers take input bitstream and LAT buffer, enable the hardware for
47 decoding tasks, write the result to LAT buffer, and disable the hardware
48 after the LAT decoding is done.
50 Its workers take LAT buffer and output buffer, enable the hardware for
56 The hardware might be associated with different SMI-common devices.
58 the unique SMI-common device must be placed under a separate parent node in
61 LAT-SoC refers to another hardware block that connected to additional LARB
63 It requires independent power and clock control to work with LAT decoder, and
67 MT8195: LAT-SoC + LAT + Core
68 MT8192: LAT + Core
69 MT8188: LAT + Core
75 - mediatek,mt8192-vcodec-dec
76 - mediatek,mt8186-vcodec-dec
77 - mediatek,mt8188-vcodec-dec
78 - mediatek,mt8195-vcodec-dec
83 - description: VDEC_SYS register space
84 - description: VDEC_RACING_CTRL register space
99 "#address-cells":
102 "#size-cells":
109 '^video-codec@[0-9a-f]+$':
115 - mediatek,mtk-vcodec-core
116 - mediatek,mtk-vcodec-lat
117 - mediatek,mtk-vcodec-lat-soc
137 clock-names:
141 assigned-clocks:
144 assigned-clock-parents:
147 power-domains:
151 - compatible
152 - reg
153 - iommus
154 - clocks
155 - clock-names
156 - assigned-clocks
157 - assigned-clock-parents
158 - power-domains
163 - compatible
164 - reg
165 - iommus
166 - mediatek,scp
167 - ranges
174 - mediatek,mtk-vcodec-core
175 - mediatek,mtk-vcodec-lat
179 - interrupts
182 - if:
187 - mediatek,mt8192-vcodec-dec
190 clock-names:
192 - const: sel
193 - const: soc-vdec
194 - const: soc-lat
195 - const: vdec
196 - const: top
198 - if:
203 - mediatek,mt8195-vcodec-dec
206 clock-names:
208 - const: sel
209 - const: vdec
210 - const: lat
211 - const: top
216 - |
217 #include <dt-bindings/interrupt-controller/arm-gic.h>
218 #include <dt-bindings/memory/mt8192-larb-port.h>
219 #include <dt-bindings/interrupt-controller/irq.h>
220 #include <dt-bindings/clock/mt8192-clk.h>
221 #include <dt-bindings/power/mt8192-power.h>
224 #address-cells = <2>;
225 #size-cells = <2>;
228 video-codec@16000000 {
229 compatible = "mediatek,mt8192-vcodec-dec";
232 #address-cells = <2>;
233 #size-cells = <2>;
236 video-codec@10000 {
237 compatible = "mediatek,mtk-vcodec-lat";
253 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
254 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
255 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
256 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
259 video-codec@25000 {
260 compatible = "mediatek,mtk-vcodec-core";
279 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
280 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
281 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
282 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;