bindings/mailbox/fsl%2Cmu.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dong Aisheng <aisheng.dong@nxp.com>
16   for one processor to signal the other processor using interrupts.
19   different clocks (from each side of the different peripheral buses).
20   Therefore, the MU must synchronize the accesses from one side to the
22   registers (Processor A-facing, Processor B-facing).
27       - const: fsl,imx6sx-mu
28       - const: fsl,imx7ulp-mu
29       - const: fsl,imx8ulp-mu
30       - const: fsl,imx8-mu-scu
31       - const: fsl,imx8-mu-seco
32       - const: fsl,imx8ulp-mu-s4
33       - const: fsl,imx93-mu-s4
34       - const: fsl,imx95-mu
35       - const: fsl,imx95-mu-ele
36       - const: fsl,imx95-mu-v2x
37       - items:
38           - const: fsl,imx93-mu
39           - const: fsl,imx8ulp-mu
40       - items:
41           - enum:
42               - fsl,imx7s-mu
43               - fsl,imx8mq-mu
44               - fsl,imx8mm-mu
45               - fsl,imx8mn-mu
46               - fsl,imx8mp-mu
47               - fsl,imx8qm-mu
48               - fsl,imx8qxp-mu
49           - const: fsl,imx6sx-mu
50       - description: To communicate with i.MX8 SCU with fast IPC
52           - const: fsl,imx8-mu-scu
53           - enum:
54               - fsl,imx8qm-mu
55               - fsl,imx8qxp-mu
56           - const: fsl,imx6sx-mu
57       - items:
58           - enum:
59               - fsl,imx94-mu
60           - const: fsl,imx95-mu
69   interrupt-names:
72       - const: tx
73       - const: rx
75   "#mbox-cells":
84       A total of 21 channels.  Following types are
86       0 - TX channel with 32bit transmit register and IRQ transmit
88       1 - RX channel with 32bit receive register and IRQ support
89       2 - TX doorbell channel. Without own register and no ACK support.
90       3 - RX doorbell channel.
91       4 - RST channel
92       5 - Tx doorbell channel. With S/W ACK from the other side.
98   fsl,mu-side-b:
99     description: boolean, if present, means it is for side B MU.
102   power-domains:
107   '#address-cells':
110   '#size-cells':
114   "^sram@[a-f0-9]+":
119   - compatible
120   - reg
121   - interrupts
122   - "#mbox-cells"
125   - if:
129             - fsl,imx93-mu-s4
132         interrupt-names:
143           - interrupt-names
145   - if:
150               const: fsl,imx95-mu
153         "^sram@[a-f0-9]+": false
158   - |
159     #include <dt-bindings/interrupt-controller/arm-gic.h>
162         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
165         #mbox-cells = <2>;
168   - |
169     #include <dt-bindings/interrupt-controller/arm-gic.h>
172         compatible = "fsl,imx95-mu";
176         #address-cells = <1>;
177         #size-cells = <1>;
178         #mbox-cells = <2>;
181             compatible = "mmio-sram";
184             #address-cells = <1>;
185             #size-cells = <1>;
187             scmi-sram-section@0 {
188                 compatible = "arm,scmi-shmem";
192             scmi-sram-section@80 {
193                 compatible = "arm,scmi-shmem";