bindings/interrupt-controller/riscv%2Caplic.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10   - Anup Patel <anup@brainfault.org>
13   The RISC-V advanced interrupt architecture (AIA) defines an advanced
15   in a RISC-V platform. The RISC-V AIA specification can be found at
16   https://github.com/riscv/riscv-aia.
18   The RISC-V APLIC is implemented as hierarchical APLIC domains where all
24   - $ref: /schemas/interrupt-controller.yaml#
29       - enum:
30           - qemu,aplic
31       - const: riscv,aplic
36   interrupt-controller: true
38   "#interrupt-cells":
41   interrupts-extended:
46       RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
47       node, which has a CPU node (i.e. RISC-V HART) as parent.
49   msi-parent:
52       message signaled interrupt controller (IMSIC). If both "msi-parent" and
53       "interrupts-extended" properties are present then it means the APLIC
57   riscv,num-sources:
66     $ref: /schemas/types.yaml#/definitions/phandle-array
79     $ref: /schemas/types.yaml#/definitions/phandle-array
84         - description: child APLIC domain phandle
85         - description: first interrupt number of the parent APLIC domain (inclusive)
86         - description: last interrupt number of the parent APLIC domain (inclusive)
94   riscv,hart-indexes:
95     $ref: /schemas/types.yaml#/definitions/uint32-array
100       that is mentioned in the "interrupts-extended"
106   - compatible
107   - reg
108   - interrupt-controller
109   - "#interrupt-cells"
110   - riscv,num-sources
113   - required:
114       - interrupts-extended
115   - required:
116       - msi-parent
121   - |
124     interrupt-controller@c000000 {
126       interrupts-extended = <&cpu1_intc 11>,
131       interrupt-controller;
132       #interrupt-cells = <2>;
133       riscv,num-sources = <63>;
138     aplic1: interrupt-controller@d000000 {
140       interrupts-extended = <&cpu1_intc 9>,
143       interrupt-controller;
144       #interrupt-cells = <2>;
145       riscv,num-sources = <63>;
148     aplic2: interrupt-controller@e000000 {
150       interrupts-extended = <&cpu3_intc 9>,
153       interrupt-controller;
154       #interrupt-cells = <2>;
155       riscv,num-sources = <63>;
158   - |
161     interrupt-controller@c000000 {
163       msi-parent = <&imsic_mlevel>;
165       interrupt-controller;
166       #interrupt-cells = <2>;
167       riscv,num-sources = <63>;
172     aplic3: interrupt-controller@d000000 {
174       msi-parent = <&imsic_slevel>;
176       interrupt-controller;
177       #interrupt-cells = <2>;
178       riscv,num-sources = <63>;