bindings/interrupt-controller/riscv%2Caplic.yaml

4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
13   The RISC-V advanced interrupt architecture (AIA) defines an advanced
14   platform level interrupt controller (APLIC) for handling wired interrupts
19   interrupt sources connect to the root APLIC domain and a parent APLIC
20   domain can delegate interrupt sources to it's child APLIC domains. There
24   - $ref: /schemas/interrupt-controller.yaml#
36   interrupt-controller: true
38   "#interrupt-cells":
52       message signaled interrupt controller (IMSIC). If both "msi-parent" and
62       Specifies the number of wired interrupt sources supported by this
85         - description: first interrupt number of the parent APLIC domain (inclusive)
86         - description: last interrupt number of the parent APLIC domain (inclusive)
88       A interrupt delegation list where each entry is a triple consisting
89       of child APLIC domain phandle, first interrupt number of the parent
90       APLIC domain, and last interrupt number of the parent APLIC domain.
91       Firmware must configure interrupt delegation registers based on
92       interrupt delegation list.
108   - interrupt-controller
109   - "#interrupt-cells"
122     // Example 1 (APLIC domains directly injecting interrupt to HARTs):
124     interrupt-controller@c000000 {
131       interrupt-controller;
132       #interrupt-cells = <2>;
138     aplic1: interrupt-controller@d000000 {
143       interrupt-controller;
144       #interrupt-cells = <2>;
148     aplic2: interrupt-controller@e000000 {
153       interrupt-controller;
154       #interrupt-cells = <2>;
161     interrupt-controller@c000000 {
165       interrupt-controller;
166       #interrupt-cells = <2>;
172     aplic3: interrupt-controller@d000000 {
176       interrupt-controller;
177       #interrupt-cells = <2>;