Lines Matching +full:system +full:- +full:power +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX System Controller Firmware (SCFW)
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
30 Clock controller node that provides the clocks controlled by the SCU
31 $ref: /schemas/clock/fsl,scu-clk.yaml
36 $ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml
40 OCOTP controller node provided by the SCU
41 $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
46 $ref: /schemas/input/fsl,scu-key.yaml
48 reset-controller:
52 const: fsl,imx-scu-reset
53 '#reset-cells':
56 - compatible
57 - '#reset-cells'
65 channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
72 - items:
73 - description: TX0 MU channel
74 - description: RX0 MU channel
75 - items:
76 - description: TX0 MU channel
77 - description: RX0 MU channel
78 - description: optional MU channel for general interrupt
79 - items:
80 - description: TX0 MU channel
81 - description: TX1 MU channel
82 - description: TX2 MU channel
83 - description: TX3 MU channel
84 - description: RX0 MU channel
85 - description: RX1 MU channel
86 - description: RX2 MU channel
87 - description: RX3 MU channel
88 - items:
89 - description: TX0 MU channel
90 - description: TX1 MU channel
91 - description: TX2 MU channel
92 - description: TX3 MU channel
93 - description: RX0 MU channel
94 - description: RX1 MU channel
95 - description: RX2 MU channel
96 - description: RX3 MU channel
97 - description: optional MU channel for general interrupt
99 mbox-names:
101 - items:
102 - const: tx0
103 - const: rx0
104 - items:
105 - const: tx0
106 - const: rx0
107 - const: gip3
108 - items:
109 - const: tx0
110 - const: tx1
111 - const: tx2
112 - const: tx3
113 - const: rx0
114 - const: rx1
115 - const: rx2
116 - const: rx3
117 - items:
118 - const: tx0
119 - const: tx1
120 - const: tx2
121 - const: tx3
122 - const: rx0
123 - const: rx1
124 - const: rx2
125 - const: rx3
126 - const: gip3
130 Pin controller provided by the SCU
131 $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
133 power-controller:
135 Power domains controller node that provides the power domains
137 $ref: /schemas/power/fsl,scu-pd.yaml
141 RTC controller provided by the SCU
142 $ref: /schemas/rtc/fsl,scu-rtc.yaml
144 thermal-sensor:
147 $ref: /schemas/thermal/fsl,scu-thermal.yaml
151 Watchdog controller provided by the SCU
152 $ref: /schemas/watchdog/fsl,scu-wdt.yaml
155 - compatible
156 - mbox-names
157 - mboxes
162 - |
163 #include <dt-bindings/firmware/imx/rsrc.h>
164 #include <dt-bindings/input/input.h>
165 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
168 system-controller {
169 compatible = "fsl,imx-scu";
170 mbox-names = "tx0", "tx1", "tx2", "tx3",
177 clock-controller {
178 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
179 #clock-cells = <2>;
183 compatible = "fsl,imx8qxp-iomuxc";
194 compatible = "fsl,imx8qxp-scu-ocotp";
195 #address-cells = <1>;
196 #size-cells = <1>;
203 power-controller {
204 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
205 #power-domain-cells = <1>;
209 compatible = "fsl,imx8qxp-sc-rtc";
213 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
218 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
219 timeout-sec = <60>;
222 thermal-sensor {
223 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
224 #thermal-sensor-cells = <1>;