bindings/clock/qcom%2Cipq9574-nsscc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
10   - Bjorn Andersson <andersson@kernel.org>
11   - Anusha Rao <quic_anusha@quicinc.com>
15   resets on IPQ9574
18     include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19     include/dt-bindings/reset/qcom,ipq9574-nsscc.h
23     const: qcom,ipq9574-nsscc
27       - description: Board XO source
28       - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
29       - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
30       - description: GCC GPLL0 OUT AUX clock source
31       - description: Uniphy0 NSS Rx clock source
32       - description: Uniphy0 NSS Tx clock source
33       - description: Uniphy1 NSS Rx clock source
34       - description: Uniphy1 NSS Tx clock source
35       - description: Uniphy2 NSS Rx clock source
36       - description: Uniphy2 NSS Tx clock source
37       - description: GCC NSSCC clock source
39   '#interconnect-cells':
42   clock-names:
44       - const: xo
45       - const: nss_1200
46       - const: ppe_353
47       - const: gpll0_out
48       - const: uniphy0_rx
49       - const: uniphy0_tx
50       - const: uniphy1_rx
51       - const: uniphy1_tx
52       - const: uniphy2_rx
53       - const: uniphy2_tx
54       - const: bus
57   - compatible
58   - clocks
59   - clock-names
62   - $ref: qcom,gcc.yaml#
67   - |
68     #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
69     #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
70     clock-controller@39b00000 {
71       compatible = "qcom,ipq9574-nsscc";
76                <&gcc GPLL0_OUT_AUX>,
83                <&gcc GCC_NSSCC_CLK>;
84       clock-names = "xo",
95       #clock-cells = <1>;
96       #reset-cells = <1>;