Lines Matching +full:signal +full:- +full:id
1 .. SPDX-License-Identifier: GPL-2.0
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13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL (one serializer, two daisy chained deserializers)
26 | 3 - GMSL (one serializer, two deserializers)
27 | 4 - GMSL (two deserializers with two daisy chain outputs)
35 | 1 - FPDL3
36 | 2 - GMSL
44 PRODUCT-REVISION-SERIES-SERIAL
52 Input number ID, zero based.
57 | 0 - single
58 | 1 - dual (default)
61 Mapping of the incoming bits in the signal to the colour bits of the pixels.
63 | 0 - OLDI/JEIDA
64 | 1 - SPWG/VESA (default)
74 | 0 - unlocked
75 | 1 - locked
79 pixel clock is running and the DE signal is moving.
84 | 0 - not detected
85 | 1 - detected
105 | 0 - active low
106 | 1 - active high
107 | 2 - not available
115 | 0 - active low
116 | 1 - active high
117 | 2 - not available
120 If the incoming video signal does not contain synchronization VSYNC and
123 (pixels with deasserted Data Enable signal) are necessary to generate the
127 If the incoming video signal does not contain synchronization VSYNC and
130 (pixels with deasserted Data Enable signal) are necessary to generate the
144 Width of the HSYNC signal in PCLK clock ticks.
150 Width of the VSYNC signal in PCLK clock ticks.
156 Number of PCLK pulses between deassertion of the HSYNC signal and the first
164 line (marked by DE=1) and assertion of the HSYNC signal.
170 Number of video lines between deassertion of the VSYNC signal and the video
178 by DE=1) and assertion of the VSYNC signal.
189 | 0 - PLL < 50MHz (default)
190 | 1 - PLL >= 50MHz
199 Output number ID, zero based.
207 | 0 - input 0
208 | 1 - input 1
209 | 2 - v4l2 output 0
210 | 3 - v4l2 output 1
232 Output video signal frame rate limit in frames per second. Due to
235 Using this parameter one can limit the frame rate by "crippling" the signal
237 the signal appears like having the exact frame rate to the connected display.
241 HSYNC signal polarity.
243 | 0 - active low (default)
244 | 1 - active high
247 VSYNC signal polarity.
249 | 0 - active low (default)
250 | 1 - active high
253 DE signal polarity.
255 | 0 - active low
256 | 1 - active high (default)
259 Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
260 and there is a non-linear stepping between two consecutive allowed
269 Width of the HSYNC signal in pixels. The default value is 40.
272 Width of the VSYNC signal in video lines. The default value is 20.
275 Number of PCLK pulses between deassertion of the HSYNC signal and the first
280 line (marked by DE=1) and assertion of the HSYNC signal. The default value
284 Number of video lines between deassertion of the VSYNC signal and the video
289 by DE=1) and assertion of the VSYNC signal. The default value is 30.
297 | 0 - auto (default)
298 | 1 - single
299 | 2 - dual
307 | 0 - auto (default)
308 | 1 - single
309 | 2 - dual
317 | 0 - 12Gb/s (default)
318 | 1 - 6Gb/s
319 | 2 - 3Gb/s
320 | 3 - 1.5Gb/s
323 The GMSL multi-stream contains up to four video streams. This parameter
325 zero-based index of the stream. The default stream id is 0.
333 | 0 - disabled
334 | 1 - enabled (default)
337 --------------
340 - mgb4-fw.X - FPGA firmware.
341 - mgb4-data.X - Factory settings, e.g. card serial number.
343 The *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is
344 read-only. The *X* attached to the partition name represents the card number.
346 also have a third partition named *mgb4-flash* available in the system. This
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354 signal level status capability. The following scan elements are available:
359 | bit 1 - trigger 1 pending
360 | bit 2 - trigger 2 pending
361 | bit 5 - trigger 1 level
362 | bit 6 - trigger 2 level
367 The iio device can operate either in "raw" mode where you can fetch the signal
369 In the triggered buffer mode you can follow the signal level changes (activity
376 buffer mode - the values do not represent valid data in such case.*