Lines Matching full:hsync

110     The type of HSYNC pulses as detected by the video format detector.
121     HSYNC pulses, these must be generated internally in the FPGA to achieve
128     HSYNC pulses, these must be generated internally in the FPGA to achieve
131     internal HSYNC pulse. The value must be greater than 1 and smaller than
144     Width of the HSYNC signal in PCLK clock ticks.
147     the hsync field of the v4l2_bt_timings struct.
156     Number of PCLK pulses between deassertion of the HSYNC signal and the first
164     line (marked by DE=1) and assertion of the HSYNC signal.
241     HSYNC signal polarity.
269     Width of the HSYNC signal in pixels. The default value is 40.
275     Number of PCLK pulses between deassertion of the HSYNC signal and the first
280     line (marked by DE=1) and assertion of the HSYNC signal. The default value