Lines Matching full:signal

61     Mapping of the incoming bits in the signal to the colour bits of the pixels.
79     pixel clock is running and the DE signal is moving.
120     If the incoming video signal does not contain synchronization VSYNC and
123     (pixels with deasserted Data Enable signal) are necessary to generate the
127     If the incoming video signal does not contain synchronization VSYNC and
130     (pixels with deasserted Data Enable signal) are necessary to generate the
144     Width of the HSYNC signal in PCLK clock ticks.
150     Width of the VSYNC signal in PCLK clock ticks.
156     Number of PCLK pulses between deassertion of the HSYNC signal and the first
164     line (marked by DE=1) and assertion of the HSYNC signal.
170     Number of video lines between deassertion of the VSYNC signal and the video
178     by DE=1) and assertion of the VSYNC signal.
232     Output video signal frame rate limit in frames per second. Due to
235     Using this parameter one can limit the frame rate by "crippling" the signal
237     the signal appears like having the exact frame rate to the connected display.
241     HSYNC signal polarity.
247     VSYNC signal polarity.
253     DE signal polarity.
269     Width of the HSYNC signal in pixels. The default value is 40.
272     Width of the VSYNC signal in video lines. The default value is 20.
275     Number of PCLK pulses between deassertion of the HSYNC signal and the first
280     line (marked by DE=1) and assertion of the HSYNC signal. The default value
284     Number of video lines between deassertion of the VSYNC signal and the video
289     by DE=1) and assertion of the VSYNC signal. The default value is 30.
354 signal level status capability. The following scan elements are available:
367 The iio device can operate either in "raw" mode where you can fetch the signal
369 In the triggered buffer mode you can follow the signal level changes (activity