Lines Matching full:affected

11 Affected Processors
13 Below is the list of affected Intel processors [#f1]_:
36 mitigation strategy to force the CPU to clear the affected buffers before an
39 The microcode clears the affected CPU buffers when the VERW instruction is
45 before VMentry. None of the affected cores support SMT, so VERW is not required
50 Newer processors and microcode update on existing affected processors added new
54 - Bit 27 - RFDS_NO - When set, processor is not affected by RFDS.
55 - Bit 28 - RFDS_CLEAR - When set, processor is affected by RFDS, and has the
56   microcode that clears the affected buffers on VERW execution.
83      * - 'Not affected'
95 .. [#f1] Affected Processors
96 …/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-prod…