Lines Matching +full:msi +full:- +full:offset
1 .. SPDX-License-Identifier: GPL-2.0
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
40 | | <-----------------------------------> | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
59 --------------
68 scratchpad offset and number of memory windows to the host using this region.
72 .. code-block:: text
74 +------------------------+
76 +------------------------+
78 +------------------------+
80 +------------------------+
82 +------------------------+
84 +------------------------+
86 +------------------------+
88 +------------------------+
90 +------------------------+
91 | MEMORY WINDOW1 OFFSET |
92 +------------------------+
93 | SPAD OFFSET |
94 +------------------------+
96 +------------------------+
98 +------------------------+
100 +------------------------+
102 +------------------------+
104 +------------------------+
106 +------------------------+
115 MSI/MSI-X vectors (i.e., initialize the MSI/MSI-X Capability in the
118 to the MSI/MSI-X address programmed by the host. The ARGUMENT
120 lower 16 bits) and if MSI or MSI-X should be configured (BIT 16).
152 MEMORY WINDOW1 OFFSET:
157 This register will specify the offset of the memory window 1.
163 SPAD OFFSET:
168 register will specify the offset of the self scratchpad registers.
177 Used to determine the offset within the DB BAR that should be written
178 in order to raise doorbell. EPF NTB can use either MSI or MSI-X to
179 ring doorbell (MSI-X support will be added later). MSI uses same
180 address for all the interrupts and MSI-X can provide different
181 addresses for different interrupts. The MSI/MSI-X address is provided
182 by the host and the address it gives is based on the MSI/MSI-X
184 using GIC ITS will have the same MSI-X address for all the interrupts.
186 for both MSI and MSI-X, EPF NTB allocates a separate region in the
188 be mapped to the MSI/MSI-X address provided by the host. If a host
197 This holds the MSI/MSI-X data that has to be written to MSI address
202 ---------------------
214 -------------------
219 --------------
233 If one 32-bit BAR is allocated for each of these regions, the scheme would
248 be enough BARs for all the regions in a platform that supports only 64-bit
272 ----------------------------------
274 .. code-block:: text
276 +-----------------+------->+------------------+ +-----------------+
278 +-----------------+----+ +------------------+<-------+-----------------+
280 +-----------------+ +-->+------------------+<-------+-----------------+
282 +-----------------+ +-----------------+
284 +-----------------+ +-----------------+
286 +-----------------+ +-----------------+
288 +-----------------+ +-----------------+
300 ----------------------------------
302 .. code-block:: text
304 +-----------------+ +----->+----------------+-----------+-----------------+
305 | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
306 +-----------------+ | +----------------+ +-----------------+
307 | BAR1 | | | Doorbell 2 +---------+ | |
308 +-----------------+----+ +----------------+ | | |
309 | BAR2 | | Doorbell 3 +-------+ | +-----------------+
310 +-----------------+----+ +----------------+ | +-> MSI-X ADDRESS 2 |
311 | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
312 +-----------------+ | |----------------+ | | | |
313 | BAR4 | | | | | | +-----------------+
314 +-----------------+ | | MW1 +---+ | +-->+ MSI-X ADDRESS 3||
315 | BAR5 | | | | | | +-----------------+
316 +-----------------+ +----->-----------------+ | | | |
317 EP CONTROLLER 1 | | | | +-----------------+
318 | | | +---->+ MSI-X ADDRESS 4 |
319 +----------------+ | +-----------------+
322 +-------> MW1 |
325 +-----------------+
331 +-----------------+
345 ---------------------------------