12  * thread as an illegal instruction in following sequence:
23  * i.e. no illegal instruction is observed immediately after returning
88 			 * after returning from the signal handler instruction  in trap_signal_handler()
91 			 * LE endianness does in effect nothing, instruction (2)  in trap_signal_handler()
96 			 * advertently flipped, instruction (1) is tread as a  in trap_signal_handler()
97 			 * branch instruction, i.e. b .+8, hence instruction (3)  in trap_signal_handler()
108 			 * next instruction after 'tbegin.', whilst the NIP for  in trap_signal_handler()
110 			 * same address of the 'trap' instruction that generated  in trap_signal_handler()
115 				/* Go to 'success', i.e. instruction (6) */  in trap_signal_handler()
121 				 * set NIP to go to 'failure', instruction (5).  in trap_signal_handler()
156 			 * ond trap event instruction (4) (trap) was executed  in trap_signal_handler()
161 			 * event and instruction (4) was executed as 'tdi' (so  in trap_signal_handler()
163 			 * instruction (5) was taken to indicate failure and we  in trap_signal_handler()
168 			 * Flip back to BE and go to instruction (6), i.e. go to  in trap_signal_handler()
201 		 * instruction is executed on machine's native endianness (in  in ping()
204 		 * tells how a instruction is executed as a LE instruction; con-  in ping()
205 		 * versely, on a LE machine, it tells how a instruction is  in ping()
206 		 * executed as a BE instruction. When [NA] is omitted, it means  in ping()
207 		 * that the native interpretation of a given instruction is not  in ping()