Lines Matching +full:0 +full:x8000000a

98 	u64 avic_backing_page;	/* Offset 0xe0 */
99 	u8 reserved_6[8];	/* Offset 0xe8 */
100 	u64 avic_logical_id;	/* Offset 0xf0 */
101 	u64 avic_physical_id;	/* Offset 0xf8 */
106 #define TLB_CONTROL_DO_NOTHING 0
111 #define V_TPR_MASK 0x0f
120 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
134 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
150 #define SVM_VM_CR_VALID_MASK	0x001fULL
151 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
152 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
154 #define SVM_NESTED_CTL_NP_ENABLE	BIT(0)
214 #define SVM_CPUID_FUNC 0x8000000a
226 #define SVM_SELECTOR_TYPE_MASK (0xf)
239 #define INTERCEPT_CR0_READ	0
243 #define INTERCEPT_CR0_WRITE	(16 + 0)
248 #define INTERCEPT_DR0_READ	0
256 #define INTERCEPT_DR0_WRITE	(16 + 0)
265 #define SVM_EVTINJ_VEC_MASK 0xff
270 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
293 #define SVM_EXITINFO_REG_MASK 0x0F