memory-model/Documentation/explanation.txt

47 for people who want to understand how the model was designed.  It does
175 happens, the LKMM does predict this outcome can occur, and the example
215 instance, the MP example code really does sometimes yield r1 = 1 and
245 this outcome to occur, and in fact it does sometimes occur on x86 and
287 The LKMM does not work directly with the C statements that make up
432 value it obtains must somehow affect what the second event does.
550 unaligned accesses in a memory model, but the LKMM currently does not
809 	store associated with the release fence does.
848 before W' does.  However, for different CPUs C and C', it does not
925 What does it mean to say that a read-modify-write (rmw) update, such
927 this case) does not get altered between the read and the write events
1074 As mentioned above, the Alpha architecture is unique in that it does
1104 to ptr does.  And since P1 can't execute its second load
1114 ptr = &x value does, leading to the undesirable result above.  The
1175 execute before W does.
1277 to buf will propagate to P1 before the store to flag does, and the
1334 store to y does (the first cumul-fence), the store to y propagates to P2
1337 store to z does (the second cumul-fence), and P0's load executes after the
1370 propagate to Y's CPU before X does, hence before Y executes and hence
1417 because it does not start and end on the same CPU.
1449 (1)	C ends before G does, and in addition, every store that
1453 (2)	G starts before C does, and in addition, every store that
1494 starts before a grace period does then the critical section's CPU will
1497 And if a critical section ends after a grace period does then the
1554 does not imply X ->rcu-order V, because the sequence contains only
1561 before any instruction po-after F can execute.  (However, it does not
1585 that G starts before C does, but also that any write which executes on
1615 before F, just as E ->pb F does (and for much the same reasons).
1618 Guarantee by requiring that the rb relation does not contain a cycle.
1765 section in P0 both starts before P1's grace period does and ends
1766 before it does, and the critical section in P2 both starts after P1's
1767 grace period does and ends after it does.
1850 This requirement does not apply to ordinary release and acquire
1878 each CPU before W' does.  For example, consider:
1911 before the store to y does, so we cannot have r2 = 1 and r3 = 0.
2008 which may execute concurrently; if it does then the LKMM says there is
2123 the object code if the source code does not already contain a data
2129 only affects the compiler; it does not necessarily have any effect on
2149 The LKMM doesn't say much about the barrier() function, but it does
2179 This program does not contain a data race.  Although the U and V
2189 	flag does.
2201 	after the fence does and hence after Y does.
2204 executes (assuming V does execute), ruling out the possibility of a
2254 does race with a concurrent load.  Thus adding a store might create a
2334 Finally, it turns out there is a situation in which a plain write does
2359 value for x, so let's assume the READ_ONCE(x) does obtain 0.  This
2361 before the grace period in P0 does, because RCU's Grace-Period
2504 all po-earlier events against all po-later events, as smp_mb() does,
2531 what does the LKMM have to say?  Answer: It says there are no allowed