Lines Matching +full:tegra210 +full:- +full:i2s
1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra210_i2s.c - Tegra210 I2S driver
30 * On Tegra210, I2S4 has "i2s4a" and "i2s4b" pins and below update
31 * is required to select i2s4b for it to be functional for I2S
42 regmap_write(regmap, TEGRA210_I2S_SLOT_CTRL, total_slots - 1); in tegra210_i2s_set_slot_ctrl()
50 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_set_clock_rate() local
54 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); in tegra210_i2s_set_clock_rate()
56 /* No need to set rates if I2S is being operated in slave */ in tegra210_i2s_set_clock_rate()
60 err = clk_set_rate(i2s->clk_i2s, clock_rate); in tegra210_i2s_set_clock_rate()
62 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", in tegra210_i2s_set_clock_rate()
67 if (!IS_ERR(i2s->clk_sync_input)) { in tegra210_i2s_set_clock_rate()
69 * Other I/O modules in AHUB can use i2s bclk as reference in tegra210_i2s_set_clock_rate()
73 err = clk_set_rate(i2s->clk_sync_input, clock_rate); in tegra210_i2s_set_clock_rate()
76 "can't set I2S sync input rate %u, err = %d\n", in tegra210_i2s_set_clock_rate()
88 struct device *dev = compnt->dev; in tegra210_i2s_sw_reset()
89 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_sw_reset() local
106 /* Store CIF and I2S control values */ in tegra210_i2s_sw_reset()
107 regmap_read(i2s->regmap, cif_reg, &cif_ctrl); in tegra210_i2s_sw_reset()
108 regmap_read(i2s->regmap, stream_reg, &stream_ctrl); in tegra210_i2s_sw_reset()
109 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &i2s_ctrl); in tegra210_i2s_sw_reset()
112 regmap_update_bits(i2s->regmap, reset_reg, reset_mask, reset_en); in tegra210_i2s_sw_reset()
114 err = regmap_read_poll_timeout(i2s->regmap, reset_reg, val, in tegra210_i2s_sw_reset()
118 dev_err(dev, "timeout: failed to reset I2S for %s\n", in tegra210_i2s_sw_reset()
123 /* Restore CIF and I2S control values */ in tegra210_i2s_sw_reset()
124 regmap_write(i2s->regmap, cif_reg, cif_ctrl); in tegra210_i2s_sw_reset()
125 regmap_write(i2s->regmap, stream_reg, stream_ctrl); in tegra210_i2s_sw_reset()
126 regmap_write(i2s->regmap, TEGRA210_I2S_CTRL, i2s_ctrl); in tegra210_i2s_sw_reset()
134 struct snd_soc_component *compnt = snd_soc_dapm_to_component(w->dapm); in tegra210_i2s_init()
135 struct device *dev = compnt->dev; in tegra210_i2s_init()
136 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_init() local
141 switch (w->reg) { in tegra210_i2s_init()
151 return -EINVAL; in tegra210_i2s_init()
154 /* Ensure I2S is in disabled state before new session */ in tegra210_i2s_init()
155 err = regmap_read_poll_timeout(i2s->regmap, status_reg, val, in tegra210_i2s_init()
159 dev_err(dev, "timeout: previous I2S %s is still active\n", in tegra210_i2s_init()
169 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_runtime_suspend() local
171 regcache_cache_only(i2s->regmap, true); in tegra210_i2s_runtime_suspend()
172 regcache_mark_dirty(i2s->regmap); in tegra210_i2s_runtime_suspend()
174 clk_disable_unprepare(i2s->clk_i2s); in tegra210_i2s_runtime_suspend()
181 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_runtime_resume() local
184 err = clk_prepare_enable(i2s->clk_i2s); in tegra210_i2s_runtime_resume()
186 dev_err(dev, "failed to enable I2S bit clock, err: %d\n", err); in tegra210_i2s_runtime_resume()
190 regcache_cache_only(i2s->regmap, false); in tegra210_i2s_runtime_resume()
191 regcache_sync(i2s->regmap); in tegra210_i2s_runtime_resume()
196 static void tegra210_i2s_set_data_offset(struct tegra210_i2s *i2s, in tegra210_i2s_set_data_offset() argument
200 regmap_update_bits(i2s->regmap, TEGRA210_I2S_TX_CTRL, in tegra210_i2s_set_data_offset()
205 regmap_update_bits(i2s->regmap, TEGRA210_I2S_RX_CTRL, in tegra210_i2s_set_data_offset()
213 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_set_fmt() local
225 return -EINVAL; in tegra210_i2s_set_fmt()
233 tegra210_i2s_set_data_offset(i2s, 1); in tegra210_i2s_set_fmt()
238 tegra210_i2s_set_data_offset(i2s, 0); in tegra210_i2s_set_fmt()
240 /* I2S mode has data offset of 1 */ in tegra210_i2s_set_fmt()
244 tegra210_i2s_set_data_offset(i2s, 1); in tegra210_i2s_set_fmt()
257 tegra210_i2s_set_data_offset(i2s, 0); in tegra210_i2s_set_fmt()
260 return -EINVAL; in tegra210_i2s_set_fmt()
280 return -EINVAL; in tegra210_i2s_set_fmt()
283 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, mask, val); in tegra210_i2s_set_fmt()
285 i2s->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; in tegra210_i2s_set_fmt()
294 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_set_tdm_slot() local
297 i2s->tx_mask = (tx_mask > DEFAULT_I2S_SLOT_MASK) ? in tegra210_i2s_set_tdm_slot()
299 i2s->rx_mask = (rx_mask > DEFAULT_I2S_SLOT_MASK) ? in tegra210_i2s_set_tdm_slot()
308 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_set_dai_bclk_ratio() local
310 i2s->bclk_ratio = ratio; in tegra210_i2s_set_dai_bclk_ratio()
319 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_get_control() local
320 long *uctl_val = &ucontrol->value.integer.value[0]; in tegra210_i2s_get_control()
322 if (strstr(kcontrol->id.name, "Loopback")) in tegra210_i2s_get_control()
323 *uctl_val = i2s->loopback; in tegra210_i2s_get_control()
324 else if (strstr(kcontrol->id.name, "FSYNC Width")) in tegra210_i2s_get_control()
325 *uctl_val = i2s->fsync_width; in tegra210_i2s_get_control()
326 else if (strstr(kcontrol->id.name, "Capture Stereo To Mono")) in tegra210_i2s_get_control()
327 *uctl_val = i2s->stereo_to_mono[I2S_TX_PATH]; in tegra210_i2s_get_control()
328 else if (strstr(kcontrol->id.name, "Capture Mono To Stereo")) in tegra210_i2s_get_control()
329 *uctl_val = i2s->mono_to_stereo[I2S_TX_PATH]; in tegra210_i2s_get_control()
330 else if (strstr(kcontrol->id.name, "Playback Stereo To Mono")) in tegra210_i2s_get_control()
331 *uctl_val = i2s->stereo_to_mono[I2S_RX_PATH]; in tegra210_i2s_get_control()
332 else if (strstr(kcontrol->id.name, "Playback Mono To Stereo")) in tegra210_i2s_get_control()
333 *uctl_val = i2s->mono_to_stereo[I2S_RX_PATH]; in tegra210_i2s_get_control()
334 else if (strstr(kcontrol->id.name, "Playback FIFO Threshold")) in tegra210_i2s_get_control()
335 *uctl_val = i2s->rx_fifo_th; in tegra210_i2s_get_control()
336 else if (strstr(kcontrol->id.name, "BCLK Ratio")) in tegra210_i2s_get_control()
337 *uctl_val = i2s->bclk_ratio; in tegra210_i2s_get_control()
346 struct tegra210_i2s *i2s = snd_soc_component_get_drvdata(compnt); in tegra210_i2s_put_control() local
347 int value = ucontrol->value.integer.value[0]; in tegra210_i2s_put_control()
349 if (strstr(kcontrol->id.name, "Loopback")) { in tegra210_i2s_put_control()
350 i2s->loopback = value; in tegra210_i2s_put_control()
352 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, in tegra210_i2s_put_control()
354 i2s->loopback << I2S_CTRL_LPBK_SHIFT); in tegra210_i2s_put_control()
356 } else if (strstr(kcontrol->id.name, "FSYNC Width")) { in tegra210_i2s_put_control()
365 i2s->fsync_width = value; in tegra210_i2s_put_control()
367 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, in tegra210_i2s_put_control()
369 i2s->fsync_width << I2S_FSYNC_WIDTH_SHIFT); in tegra210_i2s_put_control()
371 } else if (strstr(kcontrol->id.name, "Capture Stereo To Mono")) { in tegra210_i2s_put_control()
372 i2s->stereo_to_mono[I2S_TX_PATH] = value; in tegra210_i2s_put_control()
373 } else if (strstr(kcontrol->id.name, "Capture Mono To Stereo")) { in tegra210_i2s_put_control()
374 i2s->mono_to_stereo[I2S_TX_PATH] = value; in tegra210_i2s_put_control()
375 } else if (strstr(kcontrol->id.name, "Playback Stereo To Mono")) { in tegra210_i2s_put_control()
376 i2s->stereo_to_mono[I2S_RX_PATH] = value; in tegra210_i2s_put_control()
377 } else if (strstr(kcontrol->id.name, "Playback Mono To Stereo")) { in tegra210_i2s_put_control()
378 i2s->mono_to_stereo[I2S_RX_PATH] = value; in tegra210_i2s_put_control()
379 } else if (strstr(kcontrol->id.name, "Playback FIFO Threshold")) { in tegra210_i2s_put_control()
380 i2s->rx_fifo_th = value; in tegra210_i2s_put_control()
381 } else if (strstr(kcontrol->id.name, "BCLK Ratio")) { in tegra210_i2s_put_control()
382 i2s->bclk_ratio = value; in tegra210_i2s_put_control()
393 struct tegra210_i2s *i2s = dev_get_drvdata(dev); in tegra210_i2s_set_timing_params() local
397 if (i2s->bclk_ratio) in tegra210_i2s_set_timing_params()
398 num_bclk *= i2s->bclk_ratio; in tegra210_i2s_set_timing_params()
400 if (i2s->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) in tegra210_i2s_set_timing_params()
401 tegra210_i2s_set_data_offset(i2s, num_bclk - sample_size); in tegra210_i2s_set_timing_params()
403 /* I2S bit clock rate */ in tegra210_i2s_set_timing_params()
408 dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", in tegra210_i2s_set_timing_params()
413 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); in tegra210_i2s_set_timing_params()
424 bit_count = (bclk_rate / (srate * 2)) - 1; in tegra210_i2s_set_timing_params()
427 bit_count = (bclk_rate / srate) - 1; in tegra210_i2s_set_timing_params()
429 tegra210_i2s_set_slot_ctrl(i2s->regmap, channels, in tegra210_i2s_set_timing_params()
430 i2s->tx_mask, i2s->rx_mask); in tegra210_i2s_set_timing_params()
433 dev_err(dev, "invalid I2S frame format\n"); in tegra210_i2s_set_timing_params()
434 return -EINVAL; in tegra210_i2s_set_timing_params()
438 dev_err(dev, "invalid I2S channel bit count %u\n", bit_count); in tegra210_i2s_set_timing_params()
439 return -EINVAL; in tegra210_i2s_set_timing_params()
442 regmap_write(i2s->regmap, TEGRA210_I2S_TIMING, in tegra210_i2s_set_timing_params()
452 struct device *dev = dai->dev; in tegra210_i2s_hw_params()
453 struct tegra210_i2s *i2s = snd_soc_dai_get_drvdata(dai); in tegra210_i2s_hw_params() local
461 dev_err(dev, "invalid I2S %d channel configuration\n", in tegra210_i2s_hw_params()
463 return -EINVAL; in tegra210_i2s_hw_params()
490 return -EOPNOTSUPP; in tegra210_i2s_hw_params()
494 regmap_update_bits(i2s->regmap, TEGRA210_I2S_CTRL, in tegra210_i2s_hw_params()
499 /* For playback I2S RX-CIF and for capture TX-CIF is used */ in tegra210_i2s_hw_params()
500 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in tegra210_i2s_hw_params()
505 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in tegra210_i2s_hw_params()
509 max_th = (I2S_RX_FIFO_DEPTH / cif_conf.audio_ch) - 1; in tegra210_i2s_hw_params()
511 if (i2s->rx_fifo_th > max_th) in tegra210_i2s_hw_params()
512 i2s->rx_fifo_th = max_th; in tegra210_i2s_hw_params()
514 cif_conf.threshold = i2s->rx_fifo_th; in tegra210_i2s_hw_params()
521 cif_conf.mono_conv = i2s->mono_to_stereo[path]; in tegra210_i2s_hw_params()
522 cif_conf.stereo_conv = i2s->stereo_to_mono[path]; in tegra210_i2s_hw_params()
524 tegra_set_cif(i2s->regmap, reg, &cif_conf); in tegra210_i2s_hw_params()
539 .name = "I2S-CIF",
541 .stream_name = "CIF-Playback",
550 .stream_name = "CIF-Capture",
560 .name = "I2S-DAP",
562 .stream_name = "DAP-Playback",
571 .stream_name = "DAP-Capture",
613 SOC_SINGLE_EXT("Playback FIFO Threshold", 0, 0, I2S_RX_FIFO_DEPTH - 1,
630 { "XBAR-Playback", NULL, "XBAR-TX" },
631 { "CIF-Playback", NULL, "XBAR-Playback" },
632 { "RX", NULL, "CIF-Playback" },
633 { "DAP-Playback", NULL, "RX" },
634 { "SPK", NULL, "DAP-Playback" },
636 { "XBAR-RX", NULL, "XBAR-Capture" },
637 { "XBAR-Capture", NULL, "CIF-Capture" },
638 { "CIF-Capture", NULL, "TX" },
639 { "TX", NULL, "DAP-Capture" },
640 { "DAP-Capture", NULL, "MIC" },
722 struct device *dev = &pdev->dev; in tegra210_i2s_probe()
723 struct tegra210_i2s *i2s; in tegra210_i2s_probe() local
727 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL); in tegra210_i2s_probe()
728 if (!i2s) in tegra210_i2s_probe()
729 return -ENOMEM; in tegra210_i2s_probe()
731 i2s->rx_fifo_th = DEFAULT_I2S_RX_FIFO_THRESHOLD; in tegra210_i2s_probe()
732 i2s->tx_mask = DEFAULT_I2S_SLOT_MASK; in tegra210_i2s_probe()
733 i2s->rx_mask = DEFAULT_I2S_SLOT_MASK; in tegra210_i2s_probe()
734 i2s->loopback = false; in tegra210_i2s_probe()
736 dev_set_drvdata(dev, i2s); in tegra210_i2s_probe()
738 i2s->clk_i2s = devm_clk_get(dev, "i2s"); in tegra210_i2s_probe()
739 if (IS_ERR(i2s->clk_i2s)) { in tegra210_i2s_probe()
740 dev_err(dev, "can't retrieve I2S bit clock\n"); in tegra210_i2s_probe()
741 return PTR_ERR(i2s->clk_i2s); in tegra210_i2s_probe()
746 * requires input clock from current I2S instance, which is in tegra210_i2s_probe()
749 i2s->clk_sync_input = devm_clk_get(dev, "sync_input"); in tegra210_i2s_probe()
750 if (IS_ERR(i2s->clk_sync_input)) in tegra210_i2s_probe()
751 dev_dbg(dev, "can't retrieve I2S sync input clock\n"); in tegra210_i2s_probe()
757 i2s->regmap = devm_regmap_init_mmio(dev, regs, in tegra210_i2s_probe()
759 if (IS_ERR(i2s->regmap)) { in tegra210_i2s_probe()
761 return PTR_ERR(i2s->regmap); in tegra210_i2s_probe()
764 regcache_cache_only(i2s->regmap, true); in tegra210_i2s_probe()
770 dev_err(dev, "can't register I2S component, err: %d\n", err); in tegra210_i2s_probe()
781 pm_runtime_disable(&pdev->dev); in tegra210_i2s_remove()
794 { .compatible = "nvidia,tegra210-i2s" },
801 .name = "tegra210-i2s",
811 MODULE_DESCRIPTION("Tegra210 ASoC I2S driver");