3 // tegra186_dspk.c - Tegra186 DSPK driver
33 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);  in tegra186_dspk_get_control()  local
36 		ucontrol->value.integer.value[0] = dspk->rx_fifo_th;  in tegra186_dspk_get_control()
38 		ucontrol->value.integer.value[0] = dspk->osr_val;  in tegra186_dspk_get_control()
40 		ucontrol->value.integer.value[0] = dspk->lrsel;  in tegra186_dspk_get_control()
42 		ucontrol->value.integer.value[0] = dspk->ch_sel;  in tegra186_dspk_get_control()
44 		ucontrol->value.integer.value[0] = dspk->mono_to_stereo;  in tegra186_dspk_get_control()
46 		ucontrol->value.integer.value[0] = dspk->stereo_to_mono;  in tegra186_dspk_get_control()
55 	struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);  in tegra186_dspk_put_control()  local
59 		dspk->rx_fifo_th = val;  in tegra186_dspk_put_control()
61 		dspk->osr_val = val;  in tegra186_dspk_put_control()
63 		dspk->lrsel = val;  in tegra186_dspk_put_control()
65 		dspk->ch_sel = val;  in tegra186_dspk_put_control()
67 		dspk->mono_to_stereo = val;  in tegra186_dspk_put_control()
69 		dspk->stereo_to_mono = val;  in tegra186_dspk_put_control()
76 	struct tegra186_dspk *dspk = dev_get_drvdata(dev);  in tegra186_dspk_runtime_suspend()  local
78 	regcache_cache_only(dspk->regmap, true);  in tegra186_dspk_runtime_suspend()
79 	regcache_mark_dirty(dspk->regmap);  in tegra186_dspk_runtime_suspend()
81 	clk_disable_unprepare(dspk->clk_dspk);  in tegra186_dspk_runtime_suspend()
88 	struct tegra186_dspk *dspk = dev_get_drvdata(dev);  in tegra186_dspk_runtime_resume()  local
91 	err = clk_prepare_enable(dspk->clk_dspk);  in tegra186_dspk_runtime_resume()
93 		dev_err(dev, "failed to enable DSPK clock, err: %d\n", err);  in tegra186_dspk_runtime_resume()
97 	regcache_cache_only(dspk->regmap, false);  in tegra186_dspk_runtime_resume()
98 	regcache_sync(dspk->regmap);  in tegra186_dspk_runtime_resume()
107 	struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);  in tegra186_dspk_hw_params()  local
120 	switch (dspk->ch_sel) {  in tegra186_dspk_hw_params()
129 		dev_err(dev, "Invalid DSPK client channels\n");  in tegra186_dspk_hw_params()
152 	if (dspk->rx_fifo_th > max_th)  in tegra186_dspk_hw_params()
153 		dspk->rx_fifo_th = max_th;  in tegra186_dspk_hw_params()
155 	cif_conf.threshold = dspk->rx_fifo_th;  in tegra186_dspk_hw_params()
156 	cif_conf.mono_conv = dspk->mono_to_stereo;  in tegra186_dspk_hw_params()
157 	cif_conf.stereo_conv = dspk->stereo_to_mono;  in tegra186_dspk_hw_params()
159 	tegra_set_cif(dspk->regmap, TEGRA186_DSPK_RX_CIF_CTRL,  in tegra186_dspk_hw_params()
163 	 * DSPK clock and PDM codec clock should be synchronous with 4:1 ratio,  in tegra186_dspk_hw_params()
168 	dspk_clk = (DSPK_OSR_FACTOR << dspk->osr_val) * srate * DSPK_CLK_RATIO;  in tegra186_dspk_hw_params()
170 	err = clk_set_rate(dspk->clk_dspk, dspk_clk);  in tegra186_dspk_hw_params()
172 		dev_err(dev, "can't set DSPK clock rate %u, err: %d\n",  in tegra186_dspk_hw_params()
178 	regmap_update_bits(dspk->regmap,  in tegra186_dspk_hw_params()
186 			   (dspk->osr_val << DSPK_OSR_SHIFT) |  in tegra186_dspk_hw_params()
187 			   ((dspk->ch_sel + 1) << CH_SEL_SHIFT) |  in tegra186_dspk_hw_params()
188 			   (dspk->lrsel << LRSEL_POL_SHIFT));  in tegra186_dspk_hw_params()
199 	    .name = "DSPK-CIF",
210 	    .name = "DSPK-DAP",
359 	{ .compatible = "nvidia,tegra186-dspk" },
367 	struct tegra186_dspk *dspk;  in tegra186_dspk_platform_probe()  local
371 	dspk = devm_kzalloc(dev, sizeof(*dspk), GFP_KERNEL);  in tegra186_dspk_platform_probe()
372 	if (!dspk)  in tegra186_dspk_platform_probe()
375 	dspk->osr_val = DSPK_OSR_64;  in tegra186_dspk_platform_probe()
376 	dspk->lrsel = DSPK_LRSEL_LEFT;  in tegra186_dspk_platform_probe()
377 	dspk->ch_sel = DSPK_CH_SELECT_STEREO;  in tegra186_dspk_platform_probe()
378 	dspk->mono_to_stereo = 0; /* "Zero" */  in tegra186_dspk_platform_probe()
380 	dev_set_drvdata(dev, dspk);  in tegra186_dspk_platform_probe()
382 	dspk->clk_dspk = devm_clk_get(dev, "dspk");  in tegra186_dspk_platform_probe()
383 	if (IS_ERR(dspk->clk_dspk)) {  in tegra186_dspk_platform_probe()
384 		dev_err(dev, "can't retrieve DSPK clock\n");  in tegra186_dspk_platform_probe()
385 		return PTR_ERR(dspk->clk_dspk);  in tegra186_dspk_platform_probe()
392 	dspk->regmap = devm_regmap_init_mmio(dev, regs, &tegra186_dspk_regmap);  in tegra186_dspk_platform_probe()
393 	if (IS_ERR(dspk->regmap)) {  in tegra186_dspk_platform_probe()
395 		return PTR_ERR(dspk->regmap);  in tegra186_dspk_platform_probe()
398 	regcache_cache_only(dspk->regmap, true);  in tegra186_dspk_platform_probe()
404 		dev_err(dev, "can't register DSPK component, err: %d\n",  in tegra186_dspk_platform_probe()
430 		.name = "tegra186-dspk",
441 MODULE_DESCRIPTION("Tegra186 ASoC DSPK driver");