Lines Matching +full:0 +full:x1000
83 int chan = 0; in sc7180_lpass_alloc_dma_channel()
123 return 0; in sc7180_lpass_free_dma_channel()
137 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init()
152 return 0; in sc7180_lpass_init()
161 return 0; in sc7180_lpass_exit()
165 .i2sctrl_reg_base = 0x1000,
166 .i2sctrl_reg_stride = 0x1000,
168 .irq_reg_base = 0x9000,
169 .irq_reg_stride = 0x1000,
171 .rdma_reg_base = 0xC000,
172 .rdma_reg_stride = 0x1000,
174 .hdmi_rdma_reg_base = 0x64000,
175 .hdmi_rdma_reg_stride = 0x1000,
178 .wrdma_reg_base = 0x18000,
179 .wrdma_reg_stride = 0x1000,
183 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
184 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
185 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
186 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
187 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
188 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
189 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
190 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
191 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
193 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
194 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
195 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
196 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
197 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
198 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
200 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
201 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
202 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
203 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
204 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
205 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
207 .hdmi_tx_ctl_addr = 0x1000,
208 .hdmi_legacy_addr = 0x1008,
209 .hdmi_vbit_addr = 0x610c0,
210 .hdmi_ch_lsb_addr = 0x61048,
211 .hdmi_ch_msb_addr = 0x6104c,
212 .ch_stride = 0x8,
213 .hdmi_parity_addr = 0x61034,
214 .hdmi_dmactl_addr = 0x61038,
215 .hdmi_dma_stride = 0x4,
216 .hdmi_DP_addr = 0x610c8,
217 .hdmi_sstream_addr = 0x6101c,
218 .hdmi_irq_reg_base = 0x63000,
221 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
222 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
223 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
224 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
225 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
226 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
227 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
228 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
230 .sstream_en = REG_FIELD(0x6101c, 0, 0),
231 .dma_sel = REG_FIELD(0x6101c, 1, 2),
232 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
233 .layout = REG_FIELD(0x6101c, 4, 4),
234 .layout_sp = REG_FIELD(0x6101c, 5, 8),
235 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
236 .dp_audio = REG_FIELD(0x6101c, 11, 11),
237 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
238 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
240 .mute = REG_FIELD(0x610c8, 0, 0),
241 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
242 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
243 .aif_db4 = REG_FIELD(0x610c8, 8, 15),
244 .frequency = REG_FIELD(0x610c8, 16, 21),
245 .mst_index = REG_FIELD(0x610c8, 28, 29),
246 .dptx_index = REG_FIELD(0x610c8, 30, 31),
248 .soft_reset = REG_FIELD(0x1000, 31, 31),
249 .force_reset = REG_FIELD(0x1000, 30, 30),
251 .use_hw_chs = REG_FIELD(0x61038, 0, 0),
252 .use_hw_usr = REG_FIELD(0x61038, 1, 1),
253 .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
254 .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
256 .replace_vbit = REG_FIELD(0x610c0, 0, 0),
257 .vbit_stream = REG_FIELD(0x610c0, 1, 1),
259 .legacy_en = REG_FIELD(0x1008, 0, 0),
260 .calc_en = REG_FIELD(0x61034, 0, 0),
261 .lsb_bits = REG_FIELD(0x61048, 0, 31),
262 .msb_bits = REG_FIELD(0x6104c, 0, 31),