56 	struct clk *mclk;  member
88 	 * MCLK/SCLK need to be ON early for a successful synchronization of  in platform_clock_control()
94 		/* Enable MCLK */  in platform_clock_control()
95 		ret = clk_set_rate(priv->mclk, 24000000);  in platform_clock_control()
97 			dev_err(card->dev, "Can't set rate for mclk, err: %d\n",  in platform_clock_control()
102 		ret = clk_prepare_enable(priv->mclk);  in platform_clock_control()
104 			dev_err(card->dev, "Can't enable mclk, err: %d\n", ret);  in platform_clock_control()
113 			clk_disable_unprepare(priv->mclk);  in platform_clock_control()
120 			clk_disable_unprepare(priv->mclk);  in platform_clock_control()
124 		clk_disable_unprepare(priv->mclk);  in platform_clock_control()
692 	if (IS_ERR(priv->mclk))  in kabylake_set_bias_level()
696 	 * It's required to control mclk directly in the set_bias_level  in kabylake_set_bias_level()
703 			if (!__clk_is_enabled(priv->mclk))  in kabylake_set_bias_level()
705 			dev_dbg(card->dev, "Disable mclk");  in kabylake_set_bias_level()
706 			clk_disable_unprepare(priv->mclk);  in kabylake_set_bias_level()
708 			dev_dbg(card->dev, "Enable mclk");  in kabylake_set_bias_level()
709 			ret = clk_set_rate(priv->mclk, 24000000);  in kabylake_set_bias_level()
711 				dev_err(card->dev, "Can't set rate for mclk, err: %d\n",  in kabylake_set_bias_level()
716 			ret = clk_prepare_enable(priv->mclk);  in kabylake_set_bias_level()
718 				dev_err(card->dev, "Can't enable mclk, err: %d\n",  in kabylake_set_bias_level()
721 				/* mclk is already enabled in FW */  in kabylake_set_bias_level()
805 	ctx->mclk = devm_clk_get(&pdev->dev, "ssp1_mclk");  in kabylake_audio_probe()
806 	if (IS_ERR(ctx->mclk)) {  in kabylake_audio_probe()
807 		ret = PTR_ERR(ctx->mclk);  in kabylake_audio_probe()