26 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
33 	struct clk *mclk;  member
64 		if (ctx->mclk) {  in platform_clock_control()
65 			ret = clk_prepare_enable(ctx->mclk);  in platform_clock_control()
68 					"could not configure MCLK state");  in platform_clock_control()
73 		/* set codec PLL source to the 19.2MHz platform clock (MCLK) */  in platform_clock_control()
90 		 * PLL will be off when idle and MCLK will also be off by ACPI  in platform_clock_control()
97 		if (ctx->mclk)  in platform_clock_control()
98 			clk_disable_unprepare(ctx->mclk);  in platform_clock_control()
150 	/* set codec PLL source to the 19.2MHz platform clock (MCLK) */  in cht_aif1_hw_params()
214 	if (ctx->mclk) {  in cht_codec_init()
225 		ret = clk_prepare_enable(ctx->mclk);  in cht_codec_init()
227 			clk_disable_unprepare(ctx->mclk);  in cht_codec_init()
229 		ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);  in cht_codec_init()
232 			dev_err(runtime->dev, "unable to set MCLK rate\n");  in cht_codec_init()
452 	drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");  in snd_cht_mc_probe()
453 	if (IS_ERR(drv->mclk)) {  in snd_cht_mc_probe()
455 			"Failed to get MCLK from pmc_plt_clk_3: %ld\n",  in snd_cht_mc_probe()
456 			PTR_ERR(drv->mclk));  in snd_cht_mc_probe()
457 		return PTR_ERR(drv->mclk);  in snd_cht_mc_probe()