Lines Matching +full:imx8mq +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #include "imx-pcm.h"
41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
61 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_isr()
62 struct device *dev = &sai->pdev->dev; in fsl_sai_isr()
74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); in fsl_sai_isr()
90 /* FIFO reset for safety */ in fsl_sai_isr()
104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); in fsl_sai_isr()
108 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); in fsl_sai_isr()
124 /* FIFO reset for safety */ in fsl_sai_isr()
138 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); in fsl_sai_isr()
152 sai->slots = slots; in fsl_sai_set_dai_tdm_slot()
153 sai->slot_width = slot_width; in fsl_sai_set_dai_tdm_slot()
163 sai->bclk_ratio = ratio; in fsl_sai_set_dai_bclk_ratio()
172 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_sysclk_tr()
190 return -EINVAL; in fsl_sai_set_dai_sysclk_tr()
193 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_sysclk_tr()
210 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
217 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
226 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_fmt_tr()
230 if (!sai->is_lsb_first) in fsl_sai_set_dai_fmt_tr()
261 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
269 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
274 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
296 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
304 sai->is_slave_mode = false; in fsl_sai_set_dai_fmt_tr()
307 sai->is_slave_mode = true; in fsl_sai_set_dai_fmt_tr()
311 sai->is_slave_mode = false; in fsl_sai_set_dai_fmt_tr()
315 sai->is_slave_mode = true; in fsl_sai_set_dai_fmt_tr()
318 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
321 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_fmt_tr()
323 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_set_dai_fmt_tr()
336 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); in fsl_sai_set_dai_fmt()
342 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); in fsl_sai_set_dai_fmt()
350 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_bclk()
359 if (sai->is_slave_mode) in fsl_sai_set_bclk()
363 clk_rate = clk_get_rate(sai->mclk_clk[id]); in fsl_sai_set_bclk()
369 ret = clk_rate - ratio * freq; in fsl_sai_set_bclk()
378 dev_dbg(dai->dev, in fsl_sai_set_bclk()
389 sai->mclk_id[tx] = id; in fsl_sai_set_bclk()
398 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", in fsl_sai_set_bclk()
400 return -EINVAL; in fsl_sai_set_bclk()
414 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), in fsl_sai_set_bclk()
416 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); in fsl_sai_set_bclk()
417 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), in fsl_sai_set_bclk()
418 FSL_SAI_CR2_DIV_MASK, savediv - 1); in fsl_sai_set_bclk()
419 } else if (!sai->synchronous[dir]) { in fsl_sai_set_bclk()
420 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
422 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); in fsl_sai_set_bclk()
423 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
424 FSL_SAI_CR2_DIV_MASK, savediv - 1); in fsl_sai_set_bclk()
427 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", in fsl_sai_set_bclk()
428 sai->mclk_id[tx], savediv, savesub); in fsl_sai_set_bclk()
438 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_params()
439 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_params()
449 if (sai->slots) in fsl_sai_hw_params()
450 slots = sai->slots; in fsl_sai_hw_params()
452 if (sai->slot_width) in fsl_sai_hw_params()
453 slot_width = sai->slot_width; in fsl_sai_hw_params()
457 if (!sai->is_slave_mode) { in fsl_sai_hw_params()
458 if (sai->bclk_ratio) in fsl_sai_hw_params()
460 sai->bclk_ratio * in fsl_sai_hw_params()
470 if (!(sai->mclk_streams & BIT(substream->stream))) { in fsl_sai_hw_params()
471 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_params()
475 sai->mclk_streams |= BIT(substream->stream); in fsl_sai_hw_params()
479 if (!sai->is_dsp_mode) in fsl_sai_hw_params()
485 if (sai->is_lsb_first) in fsl_sai_hw_params()
488 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); in fsl_sai_hw_params()
492 /* Set to output mode to avoid tri-stated data pins */ in fsl_sai_hw_params()
502 if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) { in fsl_sai_hw_params()
503 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), in fsl_sai_hw_params()
507 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), in fsl_sai_hw_params()
512 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_params()
514 FSL_SAI_CR3_TRCE((1 << pins) - 1)); in fsl_sai_hw_params()
515 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
519 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), in fsl_sai_hw_params()
522 regmap_write(sai->regmap, FSL_SAI_xMR(tx), in fsl_sai_hw_params()
523 ~0UL - ((1 << min(channels, slots)) - 1)); in fsl_sai_hw_params()
532 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_free()
533 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_free()
535 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_free()
538 if (!sai->is_slave_mode && in fsl_sai_hw_free()
539 sai->mclk_streams & BIT(substream->stream)) { in fsl_sai_hw_free()
540 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_free()
541 sai->mclk_streams &= ~BIT(substream->stream); in fsl_sai_hw_free()
549 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_config_disable()
553 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
559 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); in fsl_sai_config_disable()
560 } while (--count && xcsr & FSL_SAI_CSR_TERE); in fsl_sai_config_disable()
562 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
568 * anymore. Add software reset to fix this issue. in fsl_sai_config_disable()
572 if (!sai->is_slave_mode) { in fsl_sai_config_disable()
573 /* Software Reset */ in fsl_sai_config_disable()
574 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); in fsl_sai_config_disable()
575 /* Clear SR bit to finish the reset */ in fsl_sai_config_disable()
576 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); in fsl_sai_config_disable()
584 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_trigger()
586 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_trigger()
596 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
597 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
598 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
599 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
609 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
612 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
626 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), in fsl_sai_trigger()
629 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
635 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
637 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
641 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); in fsl_sai_trigger()
661 return -EINVAL; in fsl_sai_trigger()
671 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_startup()
678 if (sai->soc_data->use_edma) in fsl_sai_startup()
679 snd_pcm_hw_constraint_step(substream->runtime, 0, in fsl_sai_startup()
681 tx ? sai->dma_params_tx.maxburst : in fsl_sai_startup()
682 sai->dma_params_rx.maxburst); in fsl_sai_startup()
684 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, in fsl_sai_startup()
703 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); in fsl_sai_dai_probe()
704 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_dai_probe()
706 /* Software Reset for both Tx and Rx */ in fsl_sai_dai_probe()
707 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
708 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
709 /* Clear SR bit to finish the reset */ in fsl_sai_dai_probe()
710 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_dai_probe()
711 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_dai_probe()
713 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), in fsl_sai_dai_probe()
714 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
715 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); in fsl_sai_dai_probe()
716 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), in fsl_sai_dai_probe()
717 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
718 FSL_SAI_MAXBURST_RX - 1); in fsl_sai_dai_probe()
720 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, in fsl_sai_dai_probe()
721 &sai->dma_params_rx); in fsl_sai_dai_probe()
731 .stream_name = "CPU-Playback",
740 .stream_name = "CPU-Capture",
752 .name = "fsl-sai",
806 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_readable_reg()
862 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_volatile_reg()
905 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_writeable_reg()
952 unsigned char ofs = sai->soc_data->reg_offset; in fsl_sai_check_version()
959 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); in fsl_sai_check_version()
965 sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >> in fsl_sai_check_version()
967 sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >> in fsl_sai_check_version()
969 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; in fsl_sai_check_version()
971 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); in fsl_sai_check_version()
978 sai->param.slot_num = 1 << in fsl_sai_check_version()
982 sai->param.fifo_depth = 1 << in fsl_sai_check_version()
986 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; in fsl_sai_check_version()
993 struct device_node *np = pdev->dev.of_node; in fsl_sai_probe()
1002 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); in fsl_sai_probe()
1004 return -ENOMEM; in fsl_sai_probe()
1006 sai->pdev = pdev; in fsl_sai_probe()
1007 sai->soc_data = of_device_get_match_data(&pdev->dev); in fsl_sai_probe()
1009 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); in fsl_sai_probe()
1012 base = devm_ioremap_resource(&pdev->dev, res); in fsl_sai_probe()
1016 if (sai->soc_data->reg_offset == 8) { in fsl_sai_probe()
1023 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, in fsl_sai_probe()
1027 if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER) in fsl_sai_probe()
1028 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, in fsl_sai_probe()
1030 if (IS_ERR(sai->regmap)) { in fsl_sai_probe()
1031 dev_err(&pdev->dev, "regmap init failed\n"); in fsl_sai_probe()
1032 return PTR_ERR(sai->regmap); in fsl_sai_probe()
1036 sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); in fsl_sai_probe()
1037 if (IS_ERR(sai->bus_clk)) { in fsl_sai_probe()
1038 dev_err(&pdev->dev, "failed to get bus clock: %ld\n", in fsl_sai_probe()
1039 PTR_ERR(sai->bus_clk)); in fsl_sai_probe()
1040 sai->bus_clk = NULL; in fsl_sai_probe()
1043 sai->mclk_clk[0] = sai->bus_clk; in fsl_sai_probe()
1046 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); in fsl_sai_probe()
1047 if (IS_ERR(sai->mclk_clk[i])) { in fsl_sai_probe()
1048 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", in fsl_sai_probe()
1049 i + 1, PTR_ERR(sai->mclk_clk[i])); in fsl_sai_probe()
1050 sai->mclk_clk[i] = NULL; in fsl_sai_probe()
1058 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED, in fsl_sai_probe()
1059 np->name, sai); in fsl_sai_probe()
1061 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); in fsl_sai_probe()
1065 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, in fsl_sai_probe()
1069 sai->synchronous[RX] = true; in fsl_sai_probe()
1070 sai->synchronous[TX] = false; in fsl_sai_probe()
1071 sai->cpu_dai_drv.symmetric_rates = 1; in fsl_sai_probe()
1072 sai->cpu_dai_drv.symmetric_channels = 1; in fsl_sai_probe()
1073 sai->cpu_dai_drv.symmetric_samplebits = 1; in fsl_sai_probe()
1075 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && in fsl_sai_probe()
1076 of_find_property(np, "fsl,sai-asynchronous", NULL)) { in fsl_sai_probe()
1078 dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); in fsl_sai_probe()
1079 return -EINVAL; in fsl_sai_probe()
1082 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { in fsl_sai_probe()
1084 sai->synchronous[RX] = false; in fsl_sai_probe()
1085 sai->synchronous[TX] = true; in fsl_sai_probe()
1086 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { in fsl_sai_probe()
1088 sai->synchronous[RX] = false; in fsl_sai_probe()
1089 sai->synchronous[TX] = false; in fsl_sai_probe()
1090 sai->cpu_dai_drv.symmetric_rates = 0; in fsl_sai_probe()
1091 sai->cpu_dai_drv.symmetric_channels = 0; in fsl_sai_probe()
1092 sai->cpu_dai_drv.symmetric_samplebits = 0; in fsl_sai_probe()
1095 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && in fsl_sai_probe()
1096 of_device_is_compatible(np, "fsl,imx6ul-sai")) { in fsl_sai_probe()
1097 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); in fsl_sai_probe()
1099 dev_err(&pdev->dev, "cannot find iomuxc registers\n"); in fsl_sai_probe()
1111 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; in fsl_sai_probe()
1112 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; in fsl_sai_probe()
1113 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; in fsl_sai_probe()
1114 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; in fsl_sai_probe()
1119 ret = fsl_sai_check_version(&pdev->dev); in fsl_sai_probe()
1121 dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret); in fsl_sai_probe()
1124 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && in fsl_sai_probe()
1125 sai->verid.major >= 3 && sai->verid.minor >= 1) { in fsl_sai_probe()
1126 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, in fsl_sai_probe()
1130 pm_runtime_enable(&pdev->dev); in fsl_sai_probe()
1131 regcache_cache_only(sai->regmap, true); in fsl_sai_probe()
1133 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, in fsl_sai_probe()
1134 &sai->cpu_dai_drv, 1); in fsl_sai_probe()
1138 if (sai->soc_data->use_imx_pcm) { in fsl_sai_probe()
1143 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in fsl_sai_probe()
1151 pm_runtime_disable(&pdev->dev); in fsl_sai_probe()
1158 pm_runtime_disable(&pdev->dev); in fsl_sai_remove()
1199 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1200 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1201 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1202 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1203 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1204 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1214 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_suspend()
1215 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_suspend()
1217 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_suspend()
1218 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_suspend()
1220 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_suspend()
1222 regcache_cache_only(sai->regmap, true); in fsl_sai_runtime_suspend()
1230 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_runtime_resume()
1233 ret = clk_prepare_enable(sai->bus_clk); in fsl_sai_runtime_resume()
1239 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { in fsl_sai_runtime_resume()
1240 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1245 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { in fsl_sai_runtime_resume()
1246 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1251 regcache_cache_only(sai->regmap, false); in fsl_sai_runtime_resume()
1252 regcache_mark_dirty(sai->regmap); in fsl_sai_runtime_resume()
1253 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1254 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1256 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_runtime_resume()
1257 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_runtime_resume()
1259 ret = regcache_sync(sai->regmap); in fsl_sai_runtime_resume()
1266 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_resume()
1267 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1269 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_resume()
1270 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1272 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_resume()
1289 .name = "fsl-sai",
1298 MODULE_ALIAS("platform:fsl-sai");