24 /* ASRC Context Control Extended 2 */
70 /* ASRC Channel Status 2 */
100 #define EASRC_CC_FIFO_WTMK(v)		(((v) << EASRC_CC_FIFO_WTMK_SHIFT) \  argument
106 #define EASRC_CC_SAMPLE_POS(v)		(((v) << EASRC_CC_SAMPLE_POS_SHIFT) \  argument
112 #define EASRC_CC_BPS_WIDTH		2
115 #define EASRC_CC_BPS(v)			(((v) << EASRC_CC_BPS_SHIFT) \  argument
127 #define EASRC_CC_CHEN(v)		(((v) << EASRC_CC_CHEN_SHIFT) \  argument
141 #define EASRC_CCE1_PF_EXP(v)		(((v) << EASRC_CCE1_PF_EXP_SHIFT) \  argument
161 #define EASRC_CCE1_RS_INIT_SHIFT	2
162 #define EASRC_CCE1_RS_INIT_WIDTH	2
165 #define EASRC_CCE1_RS_INIT(v)		(((v) << EASRC_CCE1_RS_INIT_SHIFT) \  argument
168 #define EASRC_CCE1_PF_INIT_WIDTH	2
171 #define EASRC_CCE1_PF_INIT(v)		(((v) << EASRC_CCE1_PF_INIT_SHIFT) \  argument
174 /* ASRC Context Control Extended 2 (CCE2) */
179 #define EASRC_CCE2_ST2_TAPS(v)		(((v) << EASRC_CCE2_ST2_TAPS_SHIFT) \  argument
185 #define EASRC_CCE2_ST1_TAPS(v)		(((v) << EASRC_CCE2_ST1_TAPS_SHIFT) \  argument
193 #define EASRC_CIA_ITER(v)		(((v) << EASRC_CIA_ITER_SHIFT) \  argument
199 #define EASRC_CIA_GRLEN(v)		(((v) << EASRC_CIA_GRLEN_SHIFT) \  argument
205 #define EASRC_CIA_ACCLEN(v)		(((v) << EASRC_CIA_ACCLEN_SHIFT) \  argument
213 #define EASRC_DPCS0R0_MAXCH(v)		(((v) << EASRC_DPCS0R0_MAXCH_SHIFT) \  argument
219 #define EASRC_DPCS0R0_MINCH(v)		(((v) << EASRC_DPCS0R0_MINCH_SHIFT) \  argument
225 #define EASRC_DPCS0R0_NUMCH(v)		(((v) << EASRC_DPCS0R0_NUMCH_SHIFT) \  argument
228 #define EASRC_DPCS0R0_CTXNUM_WIDTH	2
231 #define EASRC_DPCS0R0_CTXNUM(v)		(((v) << EASRC_DPCS0R0_CTXNUM_SHIFT) \  argument
242 #define EASRC_DPCS0R1_ST1_EXP(v)	(((v) << EASRC_DPCS0R1_ST1_EXP_SHIFT) \  argument
250 #define EASRC_DPCS0R2_ST1_MA(v)		(((v) << EASRC_DPCS0R2_ST1_MA_SHIFT) \  argument
256 #define EASRC_DPCS0R2_ST1_SA(v)		(((v) << EASRC_DPCS0R2_ST1_SA_SHIFT) \  argument
264 #define EASRC_DPCS0R3_ST2_MA(v)		(((v) << EASRC_DPCS0R3_ST2_MA_SHIFT) \  argument
270 #define EASRC_DPCS0R3_ST2_SA(v)		(((v) << EASRC_DPCS0R3_ST2_SA_SHIFT) \  argument
281 #define EASRC_COC_FIFO_WTMK(v)		(((v) << EASRC_COC_FIFO_WTMK_SHIFT) \  argument
287 #define EASRC_COC_SAMPLE_POS(v)		(((v) << EASRC_COC_SAMPLE_POS_SHIFT) \  argument
293 #define EASRC_COC_BPS_WIDTH		2
296 #define EASRC_COC_BPS(v)		(((v) << EASRC_COC_BPS_SHIFT) \  argument
304 #define EASRC_COC_IEC_VDATA_SHIFT	2
319 #define EASRC_COA_ITER(v)		(((v) << EASRC_COA_ITER_SHIFT) \  argument
325 #define EASRC_COA_GRLEN(v)		(((v) << EASRC_COA_GRLEN_SHIFT) \  argument
331 #define EASRC_COA_ACCLEN(v)		(((v) << EASRC_COA_ACCLEN_SHIFT) \  argument
342 #define EASRC_SFS_NSGI(v)		(((v) << EASRC_SFS_NSGI_SHIFT) \  argument
351 #define EASRC_SFS_NSGO(v)		(((v) << EASRC_SFS_NSGO_SHIFT) \  argument
357 #define EASRC_RRL_RS_RL(v)		((v) << EASRC_RRL_RS_RL_SHIFT)  argument
367 #define EASRC_RRH_RS_RH(v)		(((v) << EASRC_RRH_RS_RH_SHIFT) \  argument
373 #define EASRC_RSUC_RS_RM(v)		((v) << EASRC_RSUC_RS_RM_SHIFT)  argument
380 #define EASRC_RRUR_RRR(v)		(((v) << EASRC_RRUR_RRR_SHIFT) \  argument
386 #define EASRC_RCTCL_RS_CL(v)		((v) << EASRC_RCTCL_RS_CL_SHIFT)  argument
391 #define EASRC_RCTCH_RS_CH(v)		((v) << EASRC_RCTCH_RS_CH_SHIFT)  argument
396 #define EASRC_PCF_CD(v)			((v) << EASRC_PCF_CD_SHIFT)  argument
401 #define EASRC_CRCM_RS_CWD(v)		((v) << EASRC_CRCM_RS_CWD_SHIFT)  argument
408 #define EASRC_CRCC_RS_CA(v)		(((v) << EASRC_CRCC_RS_CA_SHIFT) \  argument
411 #define EASRC_CRCC_RS_TAPS_WIDTH	2
414 #define EASRC_CRCC_RS_TAPS(v)		(((v) << EASRC_CRCC_RS_TAPS_SHIFT) \  argument
425 #define EASRC_IRQC_RSDM(v)		(((v) << EASRC_IRQC_RSDM_SHIFT) \  argument
431 #define EASRC_IRQC_OERM(v)		(((v) << EASRC_IRQC_OERM_SHIFT) \  argument
437 #define EASRC_IRQC_IOM(v)		(((v) << EASRC_IRQC_IOM_SHIFT) \  argument
445 #define EASRC_IRQF_RSD(v)		(((v) << EASRC_IRQF_RSD_SHIFT) \  argument
451 #define EASRC_IRQF_OER(v)		(((v) << EASRC_IRQF_OER_SHIFT) \  argument
457 #define EASRC_IRQF_IFO(v)		(((v) << EASRC_IRQF_IFO_SHIFT) \  argument
463 #define EASRC_CSx_CSx(v)		((v) << EASRC_CSx_CSx_SHIFT)  argument
470 #define EASRC_DBGC_DMS(v)		(((v) << EASRC_DBGC_DMS_SHIFT) \  argument
476 #define EASRC_DBGS_DS(v)		((v) << EASRC_DBGS_DS_SHIFT)  argument
493 #define EASRC_RS_128_TAPS		2
498 #define EASRC_INIT_MODE_ZERO_FILL	2
520 	EASRC_WIDTH_24_BIT = 2,
556 	unsigned int width : 2;
592  * @st2_num_taps: tap number of stage 2
599  * @st2_coeff: pointer of stage 2 coeff
639 	struct fsl_easrc_slot slot[EASRC_CTX_MAX_NUM][2];