46 	if (ret < 0) {  in rt715_index_write()
62 	if (ret < 0)  in rt715_get_gain()
66 	val_h |= 0x20;  in rt715_get_gain()
69 	if (ret < 0)  in rt715_get_gain()
91 		val_h = 0x80;  in rt715_set_amp_gain_put()
93 		val_h = 0x0;  in rt715_set_amp_gain_put()
100 		val_ll = (mc->max - ucontrol->value.integer.value[0]) << 7;  in rt715_set_amp_gain_put()
102 		read_ll = read_ll & 0x7f;  in rt715_set_amp_gain_put()
106 		val_ll = ((ucontrol->value.integer.value[0]) & 0x7f);  in rt715_set_amp_gain_put()
110 		read_ll = read_ll & 0x80;  in rt715_set_amp_gain_put()
121 		read_rl = read_rl & 0x7f;  in rt715_set_amp_gain_put()
125 		val_lr = ((ucontrol->value.integer.value[1]) & 0x7f);  in rt715_set_amp_gain_put()
129 		read_rl = read_rl & 0x80;  in rt715_set_amp_gain_put()
133 	for (i = 0; i < 3; i++) { /* retry 3 times at most */  in rt715_set_amp_gain_put()
154 			val_h = 0x80;  in rt715_set_amp_gain_put()
156 			val_h = 0x0;  in rt715_set_amp_gain_put()
167 	return 0;  in rt715_set_amp_gain_put()
183 		val_h = 0x80;  in rt715_set_amp_gain_get()
185 		val_h = 0x0;  in rt715_set_amp_gain_get()
191 		read_ll = !((read_ll & 0x80) >> RT715_MUTE_SFT);  in rt715_set_amp_gain_get()
192 		read_rl = !((read_rl & 0x80) >> RT715_MUTE_SFT);  in rt715_set_amp_gain_get()
195 		read_ll = read_ll & 0x7f;  in rt715_set_amp_gain_get()
196 		read_rl = read_rl & 0x7f;  in rt715_set_amp_gain_get()
198 	ucontrol->value.integer.value[0] = read_ll;  in rt715_set_amp_gain_get()
201 	return 0;  in rt715_set_amp_gain_get()
204 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
205 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
231 			RT715_SET_GAIN_MIC_ADC_L, RT715_DIR_IN_SFT, 0x3f, 0,
235 			RT715_SET_GAIN_LINE_ADC_L, RT715_DIR_IN_SFT, 0x3f, 0,
239 			RT715_SET_GAIN_MIX_ADC_L, RT715_DIR_IN_SFT, 0x3f, 0,
243 			RT715_SET_GAIN_MIX_ADC2_L, RT715_DIR_IN_SFT, 0x3f, 0,
248 			RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0,
252 			RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0,
256 			RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0,
260 			RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0,
264 			RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0,
268 			RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0,
272 			RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0,
276 			RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0,
291 	/* nid = e->reg, vid = 0xf01 */  in rt715_mux_get()
294 	if (ret < 0) {  in rt715_mux_get()
302 	 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2.  in rt715_mux_get()
305 	if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0))  in rt715_mux_get()
307 	ucontrol->value.enumerated.item[0] = val;  in rt715_mux_get()
309 	return 0;  in rt715_mux_get()
322 	unsigned int val, val2 = 0, change, reg;  in rt715_mux_put()
325 	if (item[0] >= e->items)  in rt715_mux_put()
328 	/* Verb ID = 0x701h, nid = e->reg */  in rt715_mux_put()
329 	val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;  in rt715_mux_put()
333 	if (ret < 0) {  in rt715_mux_put()
340 		change = 0;  in rt715_mux_put()
350 						item[0], e, NULL);  in rt715_mux_put()
367  * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and
372 	0,
396 	rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text);
399 	rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text);
402 	RT715_MUX_IN3, 0, 0xf,
406 	RT715_MUX_IN4, 0, 0xf,
434 	SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0),
435 	SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0),
436 	SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0),
437 	SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0),
438 	SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
440 	SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0,
442 	SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
444 	SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
446 	SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
447 	SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0),
514 	return 0;  in rt715_set_bias_level()
534 		return 0;  in rt715_set_sdw_stream()
548 	return 0;  in rt715_set_sdw_stream()
573 	unsigned int val = 0;  in rt715_pcm_hw_params()
587 		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500);  in rt715_pcm_hw_params()
592 		rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000);  in rt715_pcm_hw_params()
616 	/* bit 14 0:48K 1:44.1K */  in rt715_pcm_hw_params()
617 	/* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */  in rt715_pcm_hw_params()
619 		val |= 0x40 << 8;  in rt715_pcm_hw_params()
622 		val |= 0x0 << 8;  in rt715_pcm_hw_params()
631 		/* bit 3:0 Number of Channel */  in rt715_pcm_hw_params()
644 		val |= (0x1 << 4);  in rt715_pcm_hw_params()
647 		val |= (0x2 << 4);  in rt715_pcm_hw_params()
650 		val |= (0x3 << 4);  in rt715_pcm_hw_params()
653 		val |= (0x4 << 4);  in rt715_pcm_hw_params()
679 	return 0;  in rt715_pcm_hw_free()
737 		value = 0x0;  in rt715_clock_config()
740 		value = 0x1;  in rt715_clock_config()
743 		value = 0x2;  in rt715_clock_config()
746 		value = 0x3;  in rt715_clock_config()
749 		value = 0x4;  in rt715_clock_config()
752 		value = 0x5;  in rt715_clock_config()
758 	regmap_write(rt715->regmap, 0xe0, value);  in rt715_clock_config()
759 	regmap_write(rt715->regmap, 0xf0, value);  in rt715_clock_config()
761 	return 0;  in rt715_clock_config()
799 		return 0;  in rt715_io_init()
821 	regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080);  in rt715_io_init()
822 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080);  in rt715_io_init()
824 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080);  in rt715_io_init()
825 	regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080);  in rt715_io_init()
828 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20);  in rt715_io_init()
829 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20);  in rt715_io_init()
830 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20);  in rt715_io_init()
831 	regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20);  in rt715_io_init()
833 	regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10);  in rt715_io_init()
834 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10);  in rt715_io_init()
835 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10);  in rt715_io_init()
836 	regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10);  in rt715_io_init()
838 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0);  in rt715_io_init()
839 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
840 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
841 	regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
842 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1);  in rt715_io_init()
843 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
844 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
845 	regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
846 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0);  in rt715_io_init()
847 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
848 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
849 	regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
850 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1);  in rt715_io_init()
851 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11);  in rt715_io_init()
852 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1);  in rt715_io_init()
853 	regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81);  in rt715_io_init()
869 	return 0;  in rt715_io_init()