Lines Matching full:8
326 #define RT5677_LOUT2_ENH_DRV (0x1 << 8)
327 #define RT5677_LOUT2_ENH_DRV_SFT (8)
334 #define RT5677_BST_MASK2 (0xf << 8)
335 #define RT5677_BST_SFT2 8
401 #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
402 #define RT5677_SEL_DAC4_R_SRC_SFT 8
413 #define RT5677_DAC4_L_VOL_MASK (0xff << 8)
414 #define RT5677_DAC4_L_VOL_SFT 8
419 #define RT5677_DAC3_L_VOL_MASK (0xff << 8)
420 #define RT5677_DAC3_L_VOL_SFT 8
425 #define RT5677_DAC1_L_VOL_MASK (0xff << 8)
426 #define RT5677_DAC1_L_VOL_SFT 8
431 #define RT5677_DAC2_L_VOL_MASK (0xff << 8)
432 #define RT5677_DAC2_L_VOL_SFT 8
465 #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
466 #define RT5677_STO2_ADC_L_BST_SFT 8
473 #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
474 #define RT5677_STO2_ADC_L_VOL_SFT 8
493 #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
494 #define RT5677_STO4_ADC_L_BST_SFT 8
501 #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
502 #define RT5677_STO3_ADC_L_VOL_SFT 8
507 #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
508 #define RT5677_STO4_ADC_L_VOL_SFT 8
521 #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
522 #define RT5677_SEL_STO4_DMIC_SFT 8
537 #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
538 #define RT5677_SEL_STO3_DMIC_SFT 8
553 #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
554 #define RT5677_SEL_STO2_DMIC_SFT 8
573 #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
574 #define RT5677_SEL_STO1_DMIC_SFT 8
589 #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
590 #define RT5677_SEL_MONO_DMIC_L_SFT 8
607 #define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
608 #define RT5677_DAC1_L_SEL_SFT 8
629 #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
630 #define RT5677_DAC1_R_STO_L_VOL_SFT 8
659 #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
660 #define RT5677_DAC1_L_MONO_L_VOL_SFT 8
691 #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
692 #define RT5677_DAC3_R_DD1_L_VOL_SFT 8
725 #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
726 #define RT5677_DAC4_R_DD2_L_VOL_SFT 8
767 #define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
768 #define RT5677_SEL_PDM1_R_SFT 8
792 #define RT5677_PDM1_I2C_BUSY (0x1 << 8)
816 #define RT5677_IF1_ADC3_MASK (0x3 << 8)
817 #define RT5677_IF1_ADC3_SFT 8
828 #define RT5677_IF1_DAC1_MASK (0x7 << 8)
829 #define RT5677_IF1_DAC1_SFT 8
838 #define RT5677_IF1_DAC5_MASK (0x7 << 8)
839 #define RT5677_IF1_DAC5_SFT 8
862 #define RT5677_IF2_ADC3_MASK (0x3 << 8)
863 #define RT5677_IF2_ADC3_SFT 8
874 #define RT5677_IF2_DAC1_MASK (0x7 << 8)
875 #define RT5677_IF2_DAC1_SFT 8
884 #define RT5677_IF2_DAC5_MASK (0x7 << 8)
885 #define RT5677_IF2_DAC5_SFT 8
920 #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
921 #define RT5677_DMIC_R_STO2_LH_SFT 8
922 #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
923 #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
1024 #define RT5677_PWR_DAC_M3F_R (0x1 << 8)
1025 #define RT5677_PWR_DAC_M3F_R_BIT 8
1056 #define RT5677_PWR_VREF2 (0x1 << 8)
1057 #define RT5677_PWR_VREF2_BIT 8
1080 #define RT5677_PWR_PLL2 (0x1 << 8)
1081 #define RT5677_PWR_PLL2_BIT 8
1102 #define RT5677_PWR_SR5 (0x1 << 8)
1103 #define RT5677_PWR_SR5_BIT 8
1124 #define RT5677_PWR_SR6_RDY (0x1 << 8)
1125 #define RT5677_PWR_SR6_RDY_BIT 8
1150 #define RT5677_PWR_SR7_ISO (0x1 << 8)
1151 #define RT5677_PWR_SR7_ISO_BIT 8
1179 #define RT5677_I2S_I_CP_MASK (0x3 << 8)
1180 #define RT5677_I2S_I_CP_SFT 8
1181 #define RT5677_I2S_I_CP_OFF (0x0 << 8)
1182 #define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
1183 #define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
1216 #define RT5677_I2S_PD2_MASK (0x7 << 8)
1217 #define RT5677_I2S_PD2_SFT 8
1218 #define RT5677_I2S_PD2_1 (0x0 << 8)
1219 #define RT5677_I2S_PD2_2 (0x1 << 8)
1220 #define RT5677_I2S_PD2_3 (0x2 << 8)
1221 #define RT5677_I2S_PD2_4 (0x3 << 8)
1222 #define RT5677_I2S_PD2_6 (0x4 << 8)
1223 #define RT5677_I2S_PD2_8 (0x5 << 8)
1224 #define RT5677_I2S_PD2_12 (0x6 << 8)
1225 #define RT5677_I2S_PD2_16 (0x7 << 8)
1266 #define RT5677_I2S_PD6_MASK (0x7 << 8)
1267 #define RT5677_I2S_PD6_SFT 8
1268 #define RT5677_I2S_PD6_1 (0x0 << 8)
1269 #define RT5677_I2S_PD6_2 (0x1 << 8)
1270 #define RT5677_I2S_PD6_3 (0x2 << 8)
1271 #define RT5677_I2S_PD6_4 (0x3 << 8)
1272 #define RT5677_I2S_PD6_6 (0x4 << 8)
1273 #define RT5677_I2S_PD6_8 (0x5 << 8)
1274 #define RT5677_I2S_PD6_12 (0x6 << 8)
1275 #define RT5677_I2S_PD6_16 (0x7 << 8)
1362 #define RT5677_PLL1_PD_MASK (0x1 << 8)
1363 #define RT5677_PLL1_PD_SFT 8
1364 #define RT5677_PLL1_PD_1 (0x0 << 8)
1365 #define RT5677_PLL1_PD_2 (0x1 << 8)
1397 #define RT5677_DSP_ASRC_I_SRC (0x3 << 8)
1398 #define RT5677_DSP_ASRC_I_SRC_SFT 8
1399 #define RT5677_DSP_ASRC_I_MCLK (0x0 << 8)
1400 #define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8)
1401 #define RT5677_DSP_ASRC_I_SLIM (0x2 << 8)
1402 #define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8)
1419 #define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8)
1420 #define RT5677_DA_MONO3R_CLK_SEL_SFT 8
1429 #define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8)
1430 #define RT5677_AD_STO2_CLK_SEL_SFT 8
1439 #define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8)
1440 #define RT5677_AD_MONOR_CLK_SEL_SFT 8
1445 #define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8)
1446 #define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8
1448 /* ASRC Control 8 (0x8a) */
1451 #define RT5677_I2S2_CLK_SEL_MASK (0xf << 8)
1452 #define RT5677_I2S2_CLK_SEL_SFT 8
1465 #define RT5677_VAD_BUF_OW (1 << 8)
1466 #define RT5677_VAD_BUF_OW_BIT 8
1485 #define RT5677_VAD_SRC_MASK (0x3 << 8)
1486 #define RT5677_VAD_SRC_SFT 8
1493 #define RT5677_IB23_SRC_MASK (0x7 << 8)
1494 #define RT5677_IB23_SRC_SFT 8
1503 #define RT5677_IB8_SRC_MASK (0x7 << 8)
1504 #define RT5677_IB8_SRC_SFT 8
1543 #define RT5677_INV_GPIO_JD2 (0x1 << 8)
1544 #define RT5677_INV_GPIO_JD2_SFT 8
1615 #define RT5677_GPIO3_DIR_MASK (0x1 << 8)
1616 #define RT5677_GPIO3_DIR_SFT 8
1617 #define RT5677_GPIO3_DIR_IN (0x0 << 8)
1618 #define RT5677_GPIO3_DIR_OUT (0x1 << 8)
1787 RT5677_AD_STEREO2_FILTER = (0x1 << 8),