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439 #define RT5665_L_VOL_MASK (0x3f << 8)
440 #define RT5665_L_VOL_SFT 8
445 #define RT5665_G_HP (0xf << 8)
446 #define RT5665_G_HP_SFT 8
451 #define RT5665_BST_CBJ_MASK (0xf << 8)
452 #define RT5665_BST_CBJ_SFT 8
457 #define RT5665_BST1_MASK (0x7f << 8)
458 #define RT5665_BST1_SFT 8
467 #define RT5665_BST3_MASK (0x7f << 8)
468 #define RT5665_BST3_SFT 8
475 #define RT5665_INL_VOL_MASK (0x1f << 8)
476 #define RT5665_INL_VOL_SFT 8
489 #define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
490 #define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
491 #define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
546 #define RT5665_DAC_L1_VOL_MASK (0xff << 8)
547 #define RT5665_DAC_L1_VOL_SFT 8
552 #define RT5665_DAC_L2_VOL_MASK (0xff << 8)
553 #define RT5665_DAC_L2_VOL_SFT 8
568 #define RT5665_ADC_L_VOL_MASK (0x7f << 8)
569 #define RT5665_ADC_L_VOL_SFT 8
574 #define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
575 #define RT5665_MONO_ADC_L_VOL_SFT 8
612 #define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
613 #define RT5665_STO1_DMIC_SRC_SFT 8
614 #define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
615 #define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
643 #define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
644 #define RT5665_MONO_DMIC_L_SRC_SFT 8
676 #define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
677 #define RT5665_STO2_DMIC_SRC_SFT 8
678 #define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
679 #define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
701 #define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
702 #define RT5665_DAC1_L_SEL_SFT 8
723 #define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
724 #define RT5665_G_DAC_R2_STO_L_SFT 8
757 #define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
758 #define RT5665_G_DAC_R2_MONO_L_SFT 8
791 #define RT5665_M_ST_DAC_R1 (0x1 << 8)
792 #define RT5665_M_ST_DAC_R1_SFT 8
809 #define RT5665_DAC_MIX_R_MASK (0x3 << 8)
810 #define RT5665_DAC_MIX_R_SFT 8
827 #define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
828 #define RT5665_IF2_1_ADC_SEL_SFT 8
851 #define RT5665_PDM1_R_MASK (0x3 << 8)
852 #define RT5665_PDM1_R_SFT 8
958 #define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
959 #define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
966 #define RT5665_M_DAC_L2_MA (0x1 << 8)
967 #define RT5665_M_DAC_L2_MA_SFT 8
1043 #define RT5665_PWR_LDO (0x1 << 8)
1044 #define RT5665_PWR_LDO_BIT 8
1073 #define RT5665_PWR_DAC_MF_R (0x1 << 8)
1074 #define RT5665_PWR_DAC_MF_R_BIT 8
1093 #define RT5665_PWR_LM (0x1 << 8)
1094 #define RT5665_PWR_LM_BIT 8
1150 #define RT5665_PWR_BST_L (0x1 << 8)
1151 #define RT5665_PWR_BST_L_BIT 8
1194 #define RT5665_PWR_IN_R (0x1 << 8)
1195 #define RT5665_PWR_IN_R_BIT 8
1256 #define RT5665_I2S_BP_MASK (0x1 << 8)
1257 #define RT5665_I2S_BP_SFT 8
1258 #define RT5665_I2S_BP_NOR (0x0 << 8)
1259 #define RT5665_I2S_BP_INV (0x1 << 8)
1286 #define RT5665_I2S_M_PD2_MASK (0x7 << 8)
1287 #define RT5665_I2S_M_PD2_SFT 8
1288 #define RT5665_I2S_M_PD2_1 (0x0 << 8)
1289 #define RT5665_I2S_M_PD2_2 (0x1 << 8)
1290 #define RT5665_I2S_M_PD2_3 (0x2 << 8)
1291 #define RT5665_I2S_M_PD2_4 (0x3 << 8)
1292 #define RT5665_I2S_M_PD2_6 (0x4 << 8)
1293 #define RT5665_I2S_M_PD2_8 (0x5 << 8)
1294 #define RT5665_I2S_M_PD2_12 (0x6 << 8)
1295 #define RT5665_I2S_M_PD2_16 (0x7 << 8)
1331 #define RT5665_I2S_PD3_MASK (0x7 << 8)
1332 #define RT5665_I2S_PD3_SFT 8
1333 #define RT5665_I2S_PD3_1 (0x0 << 8)
1334 #define RT5665_I2S_PD3_2 (0x1 << 8)
1335 #define RT5665_I2S_PD3_3 (0x2 << 8)
1336 #define RT5665_I2S_PD3_4 (0x3 << 8)
1337 #define RT5665_I2S_PD3_6 (0x4 << 8)
1338 #define RT5665_I2S_PD3_8 (0x5 << 8)
1339 #define RT5665_I2S_PD3_12 (0x6 << 8)
1340 #define RT5665_I2S_PD3_16 (0x7 << 8)
1361 #define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
1362 #define RT5665_TDM_OUT_CH_2 (0x0 << 8)
1363 #define RT5665_TDM_OUT_CH_4 (0x1 << 8)
1364 #define RT5665_TDM_OUT_CH_6 (0x2 << 8)
1365 #define RT5665_TDM_OUT_CH_8 (0x3 << 8)
1382 #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
1391 #define RT5665_IF1_ADC3_SEL_SFT 8
1403 #define RT5665_PLL1_SRC_MASK (0x7 << 8)
1404 #define RT5665_PLL1_SRC_SFT 8
1405 #define RT5665_PLL1_SRC_MCLK (0x0 << 8)
1406 #define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
1407 #define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
1408 #define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
1447 #define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
1448 #define RT5665_DMIC_STO1_ASRC_SFT 8
1467 #define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
1468 #define RT5665_DA_STO2_CLK_SEL_SFT 8
1477 #define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
1478 #define RT5665_AD_STO2_CLK_SEL_SFT 8
1487 #define RT5665_I2S2_RATE_MASK (0xf << 8)
1488 #define RT5665_I2S2_RATE_SFT 8
1512 #define RT5665_MRES_MASK (0x3 << 8)
1513 #define RT5665_MRES_SFT 8
1514 #define RT5665_MRES_15MO (0x0 << 8)
1515 #define RT5665_MRES_25MO (0x1 << 8)
1516 #define RT5665_MRES_35MO (0x2 << 8)
1517 #define RT5665_MRES_45MO (0x3 << 8)
1532 #define RT5665_CP_FQ1_MASK (0x7 << 8)
1533 #define RT5665_CP_FQ1_SFT 8
1556 #define RT5665_PM_HP_MASK (0x3 << 8)
1557 #define RT5665_PM_HP_SFT 8
1558 #define RT5665_PM_HP_LV (0x0 << 8)
1559 #define RT5665_PM_HP_MV (0x1 << 8)
1560 #define RT5665_PM_HP_HV (0x2 << 8)
1604 #define RT5665_MIC2_OVCD_MASK (0x1 << 8)
1605 #define RT5665_MIC2_OVCD_SFT 8
1606 #define RT5665_MIC2_OVCD_DIS (0x0 << 8)
1607 #define RT5665_MIC2_OVCD_EN (0x1 << 8)
1623 #define RT5665_PWR_CLK1M_MASK (0x1 << 8)
1624 #define RT5665_PWR_CLK1M_SFT 8
1625 #define RT5665_PWR_CLK1M_PD (0x0 << 8)
1626 #define RT5665_PWR_CLK1M_PU (0x1 << 8)
1642 #define RT5665_I2S2_M_PD_MASK (0x7 << 8)
1643 #define RT5665_I2S2_M_PD_SFT 8
1659 #define RT5665_EQ_DITH_MASK (0x3 << 8)
1660 #define RT5665_EQ_DITH_SFT 8
1661 #define RT5665_EQ_DITH_NOR (0x0 << 8)
1662 #define RT5665_EQ_DITH_LSB (0x1 << 8)
1663 #define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
1664 #define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
1749 #define RT5665_GP2_OUT_MASK (0x1 << 8)
1750 #define RT5665_GP2_OUT_H (0x0 << 8)
1751 #define RT5665_GP2_OUT_L (0x1 << 8)
1800 #define RT5665_GP10_OUT_MASK (0x1 << 8)
1801 #define RT5665_GP10_OUT_H (0x0 << 8)
1802 #define RT5665_GP10_OUT_L (0x1 << 8)
1937 #define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
1938 #define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
1939 #define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)