Lines Matching full:13
287 #define RT5645_M_DAC_L2_VOL (0x1 << 13)
288 #define RT5645_M_DAC_L2_VOL_SFT 13
331 #define RT5645_M_ADC_L2 (0x1 << 13)
332 #define RT5645_M_ADC_L2_SFT 13
351 #define RT5645_M_MONO_ADC_L2 (0x1 << 13)
352 #define RT5645_M_MONO_ADC_L2_SFT 13
399 #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
400 #define RT5645_DAC_L1_STO_L_VOL_SFT 13
429 #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
430 #define RT5645_DAC_L1_MONO_L_VOL_SFT 13
457 #define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
458 #define RT5645_M_DAC_L2_DAC_L_SFT 13
505 #define RT5645_PDM1_R_MASK (0x1 << 13)
506 #define RT5645_PDM1_R_SFT 13
524 #define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)
525 #define RT5645_G_HP_L_RM_L_SFT 13
536 #define RT5645_G_BST1_RM_L_MASK (0x7 << 13)
537 #define RT5645_G_BST1_RM_L_SFT 13
556 #define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)
557 #define RT5645_G_HP_R_RM_R_SFT 13
568 #define RT5645_G_BST1_RM_R_MASK (0x7 << 13)
569 #define RT5645_G_BST1_RM_R_SFT 13
604 #define RT5645_M_HPVOL_HM (0x1 << 13)
605 #define RT5645_M_HPVOL_HM_SFT 13
657 #define RT5645_M_SV_L_SPM_L (0x1 << 13)
658 #define RT5645_M_SV_L_SPM_L_SFT 13
693 #define RT5645_G_BST3_OM_L_MASK (0x7 << 13)
694 #define RT5645_G_BST3_OM_L_SFT 13
705 #define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)
706 #define RT5645_G_DAC_R2_OM_L_SFT 13
725 #define RT5645_G_BST4_OM_R_MASK (0x7 << 13)
726 #define RT5645_G_BST4_OM_R_SFT 13
737 #define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)
738 #define RT5645_G_DAC_L2_OM_R_SFT 13
761 #define RT5645_M_OV_L_LM (0x1 << 13)
762 #define RT5645_M_OV_L_LM_SFT 13
773 #define RT5645_PWR_I2S3 (0x1 << 13)
774 #define RT5645_PWR_I2S3_BIT 13
799 #define RT5645_PWR_ADC_MF_R (0x1 << 13)
800 #define RT5645_PWR_ADC_MF_R_BIT 13
823 #define RT5645_PWR_MB (0x1 << 13)
824 #define RT5645_PWR_MB_BIT 13
849 #define RT5645_PWR_BST3 (0x1 << 13)
850 #define RT5645_PWR_BST3_BIT 13
875 #define RT5645_PWR_SM_L (0x1 << 13)
876 #define RT5645_PWR_SM_L_BIT 13
1025 #define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1026 #define RT5645_DMIC_1L_LH_SFT 13
1027 #define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)
1028 #define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1231 #define RT5645_DEPOP_MASK (0x1 << 13)
1232 #define RT5645_DEPOP_SFT 13
1233 #define RT5645_DEPOP_AUTO (0x0 << 13)
1234 #define RT5645_DEPOP_MAN (0x1 << 13)
1301 #define RT5645_MIC1_CLK_MASK (0x1 << 13)
1302 #define RT5645_MIC1_CLK_SFT 13
1303 #define RT5645_MIC1_CLK_DIS (0x0 << 13)
1304 #define RT5645_MIC1_CLK_EN (0x1 << 13)
1353 #define RT5645_EQ_CD_MASK (0x1 << 13)
1354 #define RT5645_EQ_CD_SFT 13
1355 #define RT5645_EQ_CD_DIS (0x0 << 13)
1356 #define RT5645_EQ_CD_EN (0x1 << 13)
1418 #define RT5645_DRC_AGC_UPD (0x1 << 13)
1419 #define RT5645_DRC_AGC_UPD_BIT 13
1524 #define RT5645_JD_MASK (0x7 << 13)
1525 #define RT5645_JD_SFT 13
1526 #define RT5645_JD_DIS (0x0 << 13)
1527 #define RT5645_JD_GPIO1 (0x1 << 13)
1528 #define RT5645_JD_JD1_IN4P (0x2 << 13)
1529 #define RT5645_JD_JD2_IN4N (0x3 << 13)
1530 #define RT5645_JD_GPIO2 (0x4 << 13)
1531 #define RT5645_JD_GPIO3 (0x5 << 13)
1532 #define RT5645_JD_GPIO4 (0x6 << 13)
1613 #define RT5645_JD_STKY_MASK (0x1 << 13)
1614 #define RT5645_JD_STKY_SFT 13
1615 #define RT5645_JD_STKY_DIS (0x0 << 13)
1616 #define RT5645_JD_STKY_EN (0x1 << 13)
1644 #define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1645 #define RT5645_MB1_OC_STKY_SFT 13
1646 #define RT5645_MB1_OC_STKY_DIS (0x0 << 13)
1647 #define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1862 #define RT5645_M_MP3_MASK (0x1 << 13)
1863 #define RT5645_M_MP3_SFT 13
1864 #define RT5645_M_MP3_DIS (0x0 << 13)
1865 #define RT5645_M_MP3_EN (0x1 << 13)
1878 #define RT5645_MP3_WT_MASK (0x1 << 13)
1879 #define RT5645_MP3_WT_SFT 13
1880 #define RT5645_MP3_WT_1_4 (0x0 << 13)
1881 #define RT5645_MP3_WT_1_2 (0x1 << 13)
1896 #define RT5645_3D_BT_MASK (0x1 << 13)
1897 #define RT5645_3D_BT_SFT 13
1898 #define RT5645_3D_BT_DIS (0x0 << 13)
1899 #define RT5645_3D_BT_EN (0x1 << 13)
1983 #define RT5645_OUT_SV_MASK (0x1 << 13)
1984 #define RT5645_OUT_SV_SFT 13
1985 #define RT5645_OUT_SV_DIS (0x0 << 13)
1986 #define RT5645_OUT_SV_EN (0x1 << 13)
2026 #define RT5645_3D_SPK_M_MASK (0x3 << 13)
2027 #define RT5645_3D_SPK_M_SFT 13
2060 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2061 #define RT5645_WND_WIND_SFT 13
2103 #define RT5645_RST_DSP (0x1 << 13)