Lines Matching +full:10 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
19 /* I/O - Output */
24 /* I/O - Input */
32 /* I/O - ADC/DAC/DMIC */
40 /* Mixer - D-D */
49 /* Mixer - PDM */
51 /* Mixer - ADC */
56 /* Mixer - DAC */
94 /* Format - ADC/DAC */
101 /* Format - TDM Control */
107 /* Function - Analog */
123 /* Function - Digital */
245 #define RT5645_CAPLESS_EN (0x1 << 11)
313 #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
314 #define RT5645_STO1_ADC_COMP_SFT 10
321 #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)
322 #define RT5645_MONO_ADC_COMP_SFT 10
337 #define RT5645_ADC_2_SRC_MASK (0x1 << 11)
338 #define RT5645_ADC_2_SRC_SFT 11
357 #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
358 #define RT5645_MONO_ADC_L2_SRC_SFT 11
379 #define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
380 #define RT5645_DAC1_R_SEL_SFT 10
381 #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
382 #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
383 #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
384 #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
403 #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
404 #define RT5645_DAC_L2_STO_L_VOL_SFT 11
405 #define RT5645_M_ANC_DAC_L (0x1 << 10)
406 #define RT5645_M_ANC_DAC_L_SFT 10
433 #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
434 #define RT5645_DAC_L2_MONO_L_VOL_SFT 11
435 #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
436 #define RT5645_M_DAC_R2_MONO_L_SFT 10
461 #define RT5645_M_STO_R_DAC_R (0x1 << 11)
462 #define RT5645_M_STO_R_DAC_R_SFT 11
463 #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
464 #define RT5645_STO_R_DAC_R_VOL_SFT 10
489 #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
490 #define RT5645_IF2_DAC_SEL_SFT 10
509 #define RT5645_PDM2_L_MASK (0x1 << 11)
510 #define RT5645_PDM2_L_SFT 11
511 #define RT5645_M_PDM2_L (0x1 << 10)
512 #define RT5645_M_PDM2_L_SFT 10
526 #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
527 #define RT5645_G_IN_L_RM_L_SFT 10
538 #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
539 #define RT5645_G_OM_L_RM_L_SFT 10
558 #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
559 #define RT5645_G_IN_R_RM_R_SFT 10
570 #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
571 #define RT5645_G_OM_R_RM_R_SFT 10
613 #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
614 #define RT5645_G_DAC_L1_SM_L_SFT 10
635 #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
636 #define RT5645_G_DAC_R1_SM_R_SFT 10
661 #define RT5645_M_BST3_SPM_L (0x1 << 11)
662 #define RT5645_M_BST3_SPM_L_SFT 11
675 #define RT5645_G_MONOMIX_MASK (0x1 << 10)
676 #define RT5645_G_MONOMIX_SFT 10
695 #define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
696 #define RT5645_G_BST2_OM_L_SFT 10
707 #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
708 #define RT5645_G_DAC_L2_OM_L_SFT 10
727 #define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
728 #define RT5645_G_BST2_OM_R_SFT 10
739 #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
740 #define RT5645_G_DAC_R2_OM_R_SFT 10
765 #define RT5645_G_LOUTMIX_MASK (0x1 << 11)
766 #define RT5645_G_LOUTMIX_SFT 11
777 #define RT5645_PWR_DAC_R1 (0x1 << 11)
778 #define RT5645_PWR_DAC_R1_BIT 11
803 #define RT5645_PWR_DAC_S1F (0x1 << 11)
804 #define RT5645_PWR_DAC_S1F_BIT 11
805 #define RT5645_PWR_DAC_MF_L (0x1 << 10)
806 #define RT5645_PWR_DAC_MF_L_BIT 10
827 #define RT5645_PWR_BG (0x1 << 11)
828 #define RT5645_PWR_BG_BIT 11
829 #define RT5645_PWR_MA (0x1 << 10)
830 #define RT5645_PWR_MA_BIT 10
853 #define RT5645_PWR_MB1 (0x1 << 11)
854 #define RT5645_PWR_MB1_BIT 11
855 #define RT5645_PWR_MB2 (0x1 << 10)
856 #define RT5645_PWR_MB2_BIT 10
879 #define RT5645_PWR_RM_L (0x1 << 11)
880 #define RT5645_PWR_RM_L_BIT 11
881 #define RT5645_PWR_RM_R (0x1 << 10)
882 #define RT5645_PWR_RM_R_BIT 10
897 #define RT5645_PWR_HV_L (0x1 << 11)
898 #define RT5645_PWR_HV_L_BIT 11
899 #define RT5645_PWR_HV_R (0x1 << 10)
900 #define RT5645_PWR_HV_R_BIT 10
913 #define RT5645_I2S_O_CP_MASK (0x3 << 10)
914 #define RT5645_I2S_O_CP_SFT 10
915 #define RT5645_I2S_O_CP_OFF (0x0 << 10)
916 #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
917 #define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
957 #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
958 #define RT5645_I2S_BCLK_MS2_SFT 11
959 #define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)
960 #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
1011 #define RT5645_DAHPF_EN (0x1 << 11)
1012 #define RT5645_DAHPF_EN_SFT 11
1013 #define RT5645_ADHPF_EN (0x1 << 10)
1014 #define RT5645_ADHPF_EN_SFT 10
1033 #define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1034 #define RT5645_DMIC_2_DP_SFT 10
1035 #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1036 #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1037 #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1038 #define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1069 #define RT5645_PLL1_SRC_MASK (0x7 << 11)
1070 #define RT5645_PLL1_SRC_SFT 11
1071 #define RT5645_PLL1_SRC_MCLK (0x0 << 11)
1072 #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
1073 #define RT5645_PLL1_SRC_BCLK2 (0x2 << 11)
1074 #define RT5645_PLL1_SRC_BCLK3 (0x3 << 11)
1075 #define RT5645_PLL1_SRC_RCCLK (0x4 << 11)
1095 #define RT5645_PLL_M_BP (0x1 << 11)
1096 #define RT5645_PLL_M_BP_SFT 11
1149 #define RT5645_HP_OVCD_MASK (0x1 << 10)
1150 #define RT5645_HP_OVCD_SFT 10
1151 #define RT5645_HP_OVCD_DIS (0x0 << 10)
1152 #define RT5645_HP_OVCD_EN (0x1 << 10)
1175 #define RT5645_CLSD_OM_MASK (0x1 << 11)
1176 #define RT5645_CLSD_OM_SFT 11
1177 #define RT5645_CLSD_OM_MONO (0x0 << 11)
1178 #define RT5645_CLSD_OM_STO (0x1 << 11)
1179 #define RT5645_CLSD_SCH_MASK (0x1 << 10)
1180 #define RT5645_CLSD_SCH_SFT 10
1181 #define RT5645_CLSD_SCH_L (0x0 << 10)
1182 #define RT5645_CLSD_SCH_S (0x1 << 10)
1239 #define RT5645_BPS_MASK (0x1 << 11)
1240 #define RT5645_BPS_SFT 11
1241 #define RT5645_BPS_DIS (0x0 << 11)
1242 #define RT5645_BPS_EN (0x1 << 11)
1243 #define RT5645_FAST_UPDN_MASK (0x1 << 10)
1244 #define RT5645_FAST_UPDN_SFT 10
1245 #define RT5645_FAST_UPDN_DIS (0x0 << 10)
1246 #define RT5645_FAST_UPDN_EN (0x1 << 10)
1309 #define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1310 #define RT5645_MIC1_OVCD_SFT 11
1311 #define RT5645_MIC1_OVCD_DIS (0x0 << 11)
1312 #define RT5645_MIC1_OVCD_EN (0x1 << 11)
1480 #define RT5645_ANC_SN_MASK (0x1 << 11)
1481 #define RT5645_ANC_SN_SFT 11
1482 #define RT5645_ANC_SN_DIS (0x0 << 11)
1483 #define RT5645_ANC_SN_EN (0x1 << 11)
1484 #define RT5645_ANC_CLK_MASK (0x1 << 10)
1485 #define RT5645_ANC_CLK_SFT 10
1486 #define RT5645_ANC_CLK_ANC (0x0 << 10)
1487 #define RT5645_ANC_CLK_REG (0x1 << 10)
1533 #define RT5645_JD_HP_MASK (0x1 << 11)
1534 #define RT5645_JD_HP_SFT 11
1535 #define RT5645_JD_HP_DIS (0x0 << 11)
1536 #define RT5645_JD_HP_EN (0x1 << 11)
1537 #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1538 #define RT5645_JD_HP_TRG_SFT 10
1539 #define RT5645_JD_HP_TRG_LO (0x0 << 10)
1540 #define RT5645_JD_HP_TRG_HI (0x1 << 10)
1621 #define RT5645_JD_P_MASK (0x1 << 11)
1622 #define RT5645_JD_P_SFT 11
1623 #define RT5645_JD_P_NOR (0x0 << 11)
1624 #define RT5645_JD_P_INV (0x1 << 11)
1625 #define RT5645_OT_P_MASK (0x1 << 10)
1626 #define RT5645_OT_P_SFT 10
1627 #define RT5645_OT_P_NOR (0x0 << 10)
1628 #define RT5645_OT_P_INV (0x1 << 10)
1679 #define RT5645_GP4_PIN_MASK (0x1 << 11)
1680 #define RT5645_GP4_PIN_SFT 11
1681 #define RT5645_GP4_PIN_GPIO4 (0x0 << 11)
1682 #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1683 #define RT5645_DP_SIG_MASK (0x1 << 10)
1684 #define RT5645_DP_SIG_SFT 10
1685 #define RT5645_DP_SIG_TEST (0x0 << 10)
1686 #define RT5645_DP_SIG_AP (0x1 << 10)
1723 #define RT5645_GP4_PF_MASK (0x1 << 11)
1724 #define RT5645_GP4_PF_SFT 11
1725 #define RT5645_GP4_PF_IN (0x0 << 11)
1726 #define RT5645_GP4_PF_OUT (0x1 << 11)
1727 #define RT5645_GP4_OUT_MASK (0x1 << 10)
1728 #define RT5645_GP4_OUT_SFT 10
1729 #define RT5645_GP4_OUT_LO (0x0 << 10)
1730 #define RT5645_GP4_OUT_HI (0x1 << 10)
1775 #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1776 #define RT5645_SEQ1_ST_SFT 11
1777 #define RT5645_SEQ1_ST_RUN (0x0 << 11)
1778 #define RT5645_SEQ1_ST_FIN (0x1 << 11)
1779 #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1780 #define RT5645_SEQ2_ST_SFT 10
1781 #define RT5645_SEQ2_ST_RUN (0x0 << 10)
1782 #define RT5645_SEQ2_ST_FIN (0x1 << 10)
1900 #define RT5645_3D_1F_MIX_MASK (0x3 << 11)
1901 #define RT5645_3D_1F_MIX_SFT 11
1902 #define RT5645_3D_HP_M_MASK (0x1 << 10)
1903 #define RT5645_3D_HP_M_SFT 10
1904 #define RT5645_3D_HP_M_SUR (0x0 << 10)
1905 #define RT5645_3D_HP_M_FRO (0x1 << 10)
1922 #define RT5645_1ST_HPF_MASK (0x1 << 11)
1923 #define RT5645_1ST_HPF_SFT 11
1924 #define RT5645_1ST_HPF_DIS (0x0 << 11)
1925 #define RT5645_1ST_HPF_EN (0x1 << 11)
1938 #define RT5645_SI_DAC_MASK (0x1 << 11)
1939 #define RT5645_SI_DAC_SFT 11
1940 #define RT5645_SI_DAC_AUTO (0x0 << 11)
1941 #define RT5645_SI_DAC_TEST (0x1 << 11)
1942 #define RT5645_DC_CAL_M_MASK (0x1 << 10)
1943 #define RT5645_DC_CAL_M_SFT 10
1944 #define RT5645_DC_CAL_M_CAL (0x0 << 10)
1945 #define RT5645_DC_CAL_M_NOR (0x1 << 10)
1991 #define RT5645_ZCD_DIG_MASK (0x1 << 11)
1992 #define RT5645_ZCD_DIG_SFT 11
1993 #define RT5645_ZCD_DIG_DIS (0x0 << 11)
1994 #define RT5645_ZCD_DIG_EN (0x1 << 11)
1995 #define RT5645_ZCD_MASK (0x1 << 10)
1996 #define RT5645_ZCD_SFT 10
1997 #define RT5645_ZCD_PD (0x0 << 10)
1998 #define RT5645_ZCD_PU (0x1 << 10)
2040 #define RT5645_WND_FC_NW_MASK (0x3f << 10)
2041 #define RT5645_WND_FC_NW_SFT 10
2060 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2062 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2073 #define RT5645_DP_SPK_MASK (0x1 << 10)
2074 #define RT5645_DP_SPK_SFT 10
2075 #define RT5645_DP_SPK_DIS (0x0 << 10)
2076 #define RT5645_DP_SPK_EN (0x1 << 10)
2106 #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2107 #define RT5645_IF1_ADC1_IN2_SFT 11
2108 #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2109 #define RT5645_IF1_ADC2_IN1_SFT 10
2130 #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)