Lines Matching +full:10 +full:- +full:11
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
14 #include <dt-bindings/sound/rt5640.h>
21 /* I/O - Output */
26 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
37 /* Mixer - D-D */
47 /* Mixer - ADC */
52 /* Mixer - DAC */
77 /* Format - ADC/DAC */
83 /* Function - Analog */
101 /* Function - Digital */
260 #define RT5640_ADC_COMP_MASK (0x3 << 10)
261 #define RT5640_ADC_COMP_SFT 10
272 #define RT5640_ADC_2_SRC_MASK (0x3 << 10)
273 #define RT5640_ADC_2_SRC_SFT 10
274 #define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
275 #define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
276 #define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
291 #define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
292 #define RT5640_MONO_ADC_L2_SRC_SFT 10
293 #define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
294 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
295 #define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
327 #define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
328 #define RT5640_DAC_L2_STO_L_VOL_SFT 11
329 #define RT5640_M_ANC_DAC_L (0x1 << 10)
330 #define RT5640_M_ANC_DAC_L_SFT 10
349 #define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
350 #define RT5640_DAC_L2_MONO_L_VOL_SFT 11
351 #define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
352 #define RT5640_M_DAC_R2_MONO_L_SFT 10
377 #define RT5640_M_STO_R_DAC_R (0x1 << 11)
378 #define RT5640_M_STO_R_DAC_R_SFT 11
379 #define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
380 #define RT5640_STO_R_DAC_R_VOL_SFT 10
408 #define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
409 #define RT5640_IF2_ADC_L_SEL_SFT 11
410 #define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11)
411 #define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
412 #define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
413 #define RT5640_IF2_ADC_R_SEL_SFT 10
414 #define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10)
415 #define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
454 #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
455 #define RT5640_IF2_DAC_SEL_SFT 10
456 #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
457 #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
458 #define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
459 #define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
482 #define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
483 #define RT5640_G_IN_L_RM_L_SFT 10
494 #define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
495 #define RT5640_G_OM_L_RM_L_SFT 10
514 #define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
515 #define RT5640_G_IN_R_RM_R_SFT 10
526 #define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
527 #define RT5640_G_OM_R_RM_R_SFT 10
558 #define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10)
559 #define RT5640_G_DAC_L1_SM_L_SFT 10
580 #define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10)
581 #define RT5640_G_DAC_R1_SM_R_SFT 10
606 #define RT5640_M_BST1_SPM_L (0x1 << 11)
607 #define RT5640_M_BST1_SPM_L_SFT 11
614 #define RT5640_M_BST1_SPM_R (0x1 << 11)
615 #define RT5640_M_BST1_SPM_R_SFT 11
630 #define RT5640_M_BST1_MM (0x1 << 11)
631 #define RT5640_M_BST1_MM_SFT 11
632 #define RT5640_G_MONOMIX_MASK (0x1 << 10)
633 #define RT5640_G_MONOMIX_SFT 10
638 #define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
639 #define RT5640_G_BST2_OM_L_SFT 10
650 #define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10)
651 #define RT5640_G_DAC_L2_OM_L_SFT 10
678 #define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
679 #define RT5640_G_BST2_OM_R_SFT 10
690 #define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10)
691 #define RT5640_G_DAC_R2_OM_R_SFT 10
724 #define RT5640_G_LOUTMIX_MASK (0x1 << 11)
725 #define RT5640_G_LOUTMIX_SFT 11
734 #define RT5640_PWR_DAC_R1 (0x1 << 11)
735 #define RT5640_PWR_DAC_R1_BIT 11
766 #define RT5640_PWR_BG (0x1 << 11)
767 #define RT5640_PWR_BG_BIT 11
768 #define RT5640_PWR_MM (0x1 << 10)
769 #define RT5640_PWR_MM_BIT 10
794 #define RT5640_PWR_MB1 (0x1 << 11)
795 #define RT5640_PWR_MB1_BIT 11
808 #define RT5640_PWR_RM_L (0x1 << 11)
809 #define RT5640_PWR_RM_L_BIT 11
810 #define RT5640_PWR_RM_R (0x1 << 10)
811 #define RT5640_PWR_RM_R_BIT 10
822 #define RT5640_PWR_HV_L (0x1 << 11)
823 #define RT5640_PWR_HV_L_BIT 11
824 #define RT5640_PWR_HV_R (0x1 << 10)
825 #define RT5640_PWR_HV_R_BIT 10
838 #define RT5640_I2S_O_CP_MASK (0x3 << 10)
839 #define RT5640_I2S_O_CP_SFT 10
840 #define RT5640_I2S_O_CP_OFF (0x0 << 10)
841 #define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
842 #define RT5640_I2S_O_CP_A_LAW (0x2 << 10)
886 #define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
887 #define RT5640_I2S_BCLK_MS2_SFT 11
888 #define RT5640_I2S_BCLK_MS2_32 (0x0 << 11)
889 #define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
940 #define RT5640_DAHPF_EN (0x1 << 11)
941 #define RT5640_DAHPF_EN_SFT 11
942 #define RT5640_ADHPF_EN (0x1 << 10)
943 #define RT5640_ADHPF_EN_SFT 10
962 #define RT5640_DMIC_1_DP_MASK (0x1 << 11)
963 #define RT5640_DMIC_1_DP_SFT 11
964 #define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11)
965 #define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
966 #define RT5640_DMIC_2_DP_MASK (0x1 << 10)
967 #define RT5640_DMIC_2_DP_SFT 10
968 #define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10)
969 #define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
1012 #define RT5640_PLL_M_BP (0x1 << 11)
1013 #define RT5640_PLL_M_BP_SFT 11
1058 #define RT5640_ADC_M_MASK (0x1 << 11)
1059 #define RT5640_ADC_M_SFT 11
1060 #define RT5640_ADC_M_NOR (0x0 << 11)
1061 #define RT5640_ADC_M_ASYN (0x1 << 11)
1093 #define RT5640_HP_OVCD_MASK (0x1 << 10)
1094 #define RT5640_HP_OVCD_SFT 10
1095 #define RT5640_HP_OVCD_DIS (0x0 << 10)
1096 #define RT5640_HP_OVCD_EN (0x1 << 10)
1119 #define RT5640_CLSD_OM_MASK (0x1 << 11)
1120 #define RT5640_CLSD_OM_SFT 11
1121 #define RT5640_CLSD_OM_MONO (0x0 << 11)
1122 #define RT5640_CLSD_OM_STO (0x1 << 11)
1123 #define RT5640_CLSD_SCH_MASK (0x1 << 10)
1124 #define RT5640_CLSD_SCH_SFT 10
1125 #define RT5640_CLSD_SCH_L (0x0 << 10)
1126 #define RT5640_CLSD_SCH_S (0x1 << 10)
1183 #define RT5640_BPS_MASK (0x1 << 11)
1184 #define RT5640_BPS_SFT 11
1185 #define RT5640_BPS_DIS (0x0 << 11)
1186 #define RT5640_BPS_EN (0x1 << 11)
1187 #define RT5640_FAST_UPDN_MASK (0x1 << 10)
1188 #define RT5640_FAST_UPDN_SFT 10
1189 #define RT5640_FAST_UPDN_DIS (0x0 << 10)
1190 #define RT5640_FAST_UPDN_EN (0x1 << 10)
1227 #define RT5640_OSW_L_MASK (0x1 << 11)
1228 #define RT5640_OSW_L_SFT 11
1229 #define RT5640_OSW_L_DIS (0x0 << 11)
1230 #define RT5640_OSW_L_EN (0x1 << 11)
1231 #define RT5640_OSW_R_MASK (0x1 << 10)
1232 #define RT5640_OSW_R_SFT 10
1233 #define RT5640_OSW_R_DIS (0x0 << 10)
1234 #define RT5640_OSW_R_EN (0x1 << 10)
1274 #define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1275 #define RT5640_MIC1_OVCD_SFT 11
1276 #define RT5640_MIC1_OVCD_DIS (0x0 << 11)
1277 #define RT5640_MIC1_OVCD_EN (0x1 << 11)
1434 #define RT5640_ANC_SN_MASK (0x1 << 11)
1435 #define RT5640_ANC_SN_SFT 11
1436 #define RT5640_ANC_SN_DIS (0x0 << 11)
1437 #define RT5640_ANC_SN_EN (0x1 << 11)
1438 #define RT5640_ANC_CLK_MASK (0x1 << 10)
1439 #define RT5640_ANC_CLK_SFT 10
1440 #define RT5640_ANC_CLK_ANC (0x0 << 10)
1441 #define RT5640_ANC_CLK_REG (0x1 << 10)
1487 #define RT5640_JD_HP_MASK (0x1 << 11)
1488 #define RT5640_JD_HP_SFT 11
1489 #define RT5640_JD_HP_DIS (0x0 << 11)
1490 #define RT5640_JD_HP_EN (0x1 << 11)
1491 #define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1492 #define RT5640_JD_HP_TRG_SFT 10
1493 #define RT5640_JD_HP_TRG_LO (0x0 << 10)
1494 #define RT5640_JD_HP_TRG_HI (0x1 << 10)
1575 #define RT5640_JD_P_MASK (0x1 << 11)
1576 #define RT5640_JD_P_SFT 11
1577 #define RT5640_JD_P_NOR (0x0 << 11)
1578 #define RT5640_JD_P_INV (0x1 << 11)
1579 #define RT5640_OT_P_MASK (0x1 << 10)
1580 #define RT5640_OT_P_SFT 10
1581 #define RT5640_OT_P_NOR (0x0 << 10)
1582 #define RT5640_OT_P_INV (0x1 << 10)
1593 #define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1594 #define RT5640_MB1_OC_STKY_SFT 11
1595 #define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
1596 #define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1597 #define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1598 #define RT5640_MB2_OC_STKY_SFT 10
1599 #define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
1600 #define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1635 #define RT5640_GP4_PIN_MASK (0x1 << 11)
1636 #define RT5640_GP4_PIN_SFT 11
1637 #define RT5640_GP4_PIN_GPIO4 (0x0 << 11)
1638 #define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1639 #define RT5640_DP_SIG_MASK (0x1 << 10)
1640 #define RT5640_DP_SIG_SFT 10
1641 #define RT5640_DP_SIG_TEST (0x0 << 10)
1642 #define RT5640_DP_SIG_AP (0x1 << 10)
1649 #define RT5640_GP4_PF_MASK (0x1 << 11)
1650 #define RT5640_GP4_PF_SFT 11
1651 #define RT5640_GP4_PF_IN (0x0 << 11)
1652 #define RT5640_GP4_PF_OUT (0x1 << 11)
1653 #define RT5640_GP4_OUT_MASK (0x1 << 10)
1654 #define RT5640_GP4_OUT_SFT 10
1655 #define RT5640_GP4_OUT_LO (0x0 << 10)
1656 #define RT5640_GP4_OUT_HI (0x1 << 10)
1698 /* FM34-500 Register Control 1 (0xc4) */
1701 /* FM34-500 Register Control 2 (0xc5) */
1704 /* FM34-500 Register Control 3 (0xc6) */
1717 #define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1718 #define RT5640_DSP_PD_PIN_SFT 11
1719 #define RT5640_DSP_PD_PIN_LO (0x0 << 11)
1720 #define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1721 #define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1722 #define RT5640_DSP_RST_PIN_SFT 10
1723 #define RT5640_DSP_RST_PIN_LO (0x0 << 10)
1724 #define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1739 #define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1740 #define RT5640_SEQ1_ST_SFT 11
1741 #define RT5640_SEQ1_ST_RUN (0x0 << 11)
1742 #define RT5640_SEQ1_ST_FIN (0x1 << 11)
1743 #define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1744 #define RT5640_SEQ2_ST_SFT 10
1745 #define RT5640_SEQ2_ST_RUN (0x0 << 10)
1746 #define RT5640_SEQ2_ST_FIN (0x1 << 10)
1863 #define RT5640_3D_1F_MIX_MASK (0x3 << 11)
1864 #define RT5640_3D_1F_MIX_SFT 11
1865 #define RT5640_3D_HP_M_MASK (0x1 << 10)
1866 #define RT5640_3D_HP_M_SFT 10
1867 #define RT5640_3D_HP_M_SUR (0x0 << 10)
1868 #define RT5640_3D_HP_M_FRO (0x1 << 10)
1885 #define RT5640_1ST_HPF_MASK (0x1 << 11)
1886 #define RT5640_1ST_HPF_SFT 11
1887 #define RT5640_1ST_HPF_DIS (0x0 << 11)
1888 #define RT5640_1ST_HPF_EN (0x1 << 11)
1901 #define RT5640_SI_DAC_MASK (0x1 << 11)
1902 #define RT5640_SI_DAC_SFT 11
1903 #define RT5640_SI_DAC_AUTO (0x0 << 11)
1904 #define RT5640_SI_DAC_TEST (0x1 << 11)
1905 #define RT5640_DC_CAL_M_MASK (0x1 << 10)
1906 #define RT5640_DC_CAL_M_SFT 10
1907 #define RT5640_DC_CAL_M_CAL (0x0 << 10)
1908 #define RT5640_DC_CAL_M_NOR (0x1 << 10)
1954 #define RT5640_ZCD_DIG_MASK (0x1 << 11)
1955 #define RT5640_ZCD_DIG_SFT 11
1956 #define RT5640_ZCD_DIG_DIS (0x0 << 11)
1957 #define RT5640_ZCD_DIG_EN (0x1 << 11)
1958 #define RT5640_ZCD_MASK (0x1 << 10)
1959 #define RT5640_ZCD_SFT 10
1960 #define RT5640_ZCD_PD (0x0 << 10)
1961 #define RT5640_ZCD_PU (0x1 << 10)
1984 #define RT5640_MCLK_DET (0x1 << 11)
2015 #define RT5640_WND_FC_NW_MASK (0x3f << 10)
2016 #define RT5640_WND_FC_NW_SFT 10
2035 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2037 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2048 #define RT5640_DP_SPK_MASK (0x1 << 10)
2049 #define RT5640_DP_SPK_SFT 10
2050 #define RT5640_DP_SPK_DIS (0x0 << 10)
2051 #define RT5640_DP_SPK_EN (0x1 << 10)