Lines Matching +full:0 +full:x2000
97 #define CHI32_VECTOR_BUSY 0x00000001
98 #define CHI32_STATUS_REG_HF3 0x00000008
99 #define CHI32_STATUS_REG_HF4 0x00000010
100 #define CHI32_STATUS_REG_HF5 0x00000020
101 #define CHI32_STATUS_HOST_READ_FULL 0x00000004
102 #define CHI32_STATUS_HOST_WRITE_EMPTY 0x00000002
103 #define CHI32_STATUS_IRQ 0x00000040
112 #define DSP_FNC_SET_COMMPAGE_ADDR 0x02
113 #define DSP_FNC_LOAD_LAYLA_ASIC 0xa0
114 #define DSP_FNC_LOAD_GINA24_ASIC 0xa0
115 #define DSP_FNC_LOAD_MONA_PCI_CARD_ASIC 0xa0
116 #define DSP_FNC_LOAD_LAYLA24_PCI_CARD_ASIC 0xa0
117 #define DSP_FNC_LOAD_MONA_EXTERNAL_ASIC 0xa1
118 #define DSP_FNC_LOAD_LAYLA24_EXTERNAL_ASIC 0xa1
119 #define DSP_FNC_LOAD_3G_ASIC 0xa0
129 #define MIDI_IN_STATE_NORMAL 0
151 -Set the clock select bits in the control register to 0xe (see the #define
178 #define LAYLA24_CONTINUOUS_CLOCK 0x000e
187 #define DSP_VC_RESET 0x80ff
191 #define DSP_VC_ACK_INT 0x8073
192 #define DSP_VC_SET_VMIXER_GAIN 0x0000 /* Not used, only for compile */
193 #define DSP_VC_START_TRANSFER 0x0075 /* Handshke rqd. */
194 #define DSP_VC_METERS_ON 0x0079
195 #define DSP_VC_METERS_OFF 0x007b
196 #define DSP_VC_UPDATE_OUTVOL 0x007d /* Handshke rqd. */
197 #define DSP_VC_UPDATE_INGAIN 0x007f /* Handshke rqd. */
198 #define DSP_VC_ADD_AUDIO_BUFFER 0x0081 /* Handshke rqd. */
199 #define DSP_VC_TEST_ASIC 0x00eb
200 #define DSP_VC_UPDATE_CLOCKS 0x00ef /* Handshke rqd. */
201 #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00f1 /* Handshke rqd. */
202 #define DSP_VC_SET_GD_AUDIO_STATE 0x00f1 /* Handshke rqd. */
203 #define DSP_VC_WRITE_CONTROL_REG 0x00f1 /* Handshke rqd. */
204 #define DSP_VC_MIDI_WRITE 0x00f5 /* Handshke rqd. */
205 #define DSP_VC_STOP_TRANSFER 0x00f7 /* Handshke rqd. */
206 #define DSP_VC_UPDATE_FLAGS 0x00fd /* Handshke rqd. */
207 #define DSP_VC_GO_COMATOSE 0x00f9
212 #define DSP_VC_ACK_INT 0x80F5
213 #define DSP_VC_SET_VMIXER_GAIN 0x00DB /* Handshke rqd. */
214 #define DSP_VC_START_TRANSFER 0x00DD /* Handshke rqd. */
215 #define DSP_VC_METERS_ON 0x00EF
216 #define DSP_VC_METERS_OFF 0x00F1
217 #define DSP_VC_UPDATE_OUTVOL 0x00E3 /* Handshke rqd. */
218 #define DSP_VC_UPDATE_INGAIN 0x00E5 /* Handshke rqd. */
219 #define DSP_VC_ADD_AUDIO_BUFFER 0x00E1 /* Handshke rqd. */
220 #define DSP_VC_TEST_ASIC 0x00ED
221 #define DSP_VC_UPDATE_CLOCKS 0x00E9 /* Handshke rqd. */
222 #define DSP_VC_SET_LAYLA24_FREQUENCY_REG 0x00E9 /* Handshke rqd. */
223 #define DSP_VC_SET_LAYLA_SAMPLE_RATE 0x00EB /* Handshke rqd. */
224 #define DSP_VC_SET_GD_AUDIO_STATE 0x00EB /* Handshke rqd. */
225 #define DSP_VC_WRITE_CONTROL_REG 0x00EB /* Handshke rqd. */
226 #define DSP_VC_MIDI_WRITE 0x00E7 /* Handshke rqd. */
227 #define DSP_VC_STOP_TRANSFER 0x00DF /* Handshke rqd. */
228 #define DSP_VC_UPDATE_FLAGS 0x00FB /* Handshke rqd. */
229 #define DSP_VC_GO_COMATOSE 0x00d9
251 #define DSP_FLAG_MIDI_INPUT 0x0001 /* Enable MIDI input */
252 #define DSP_FLAG_SPDIF_NONAUDIO 0x0002 /* Sets the "non-audio" bit
258 #define DSP_FLAG_PROFESSIONAL_SPDIF 0x0008 /* 1 Professional, 0 Consumer */
267 #define GLDM_CLOCK_DETECT_BIT_WORD 0x0002
268 #define GLDM_CLOCK_DETECT_BIT_SUPER 0x0004
269 #define GLDM_CLOCK_DETECT_BIT_SPDIF 0x0008
270 #define GLDM_CLOCK_DETECT_BIT_ESYNC 0x0010
279 #define GML_CLOCK_DETECT_BIT_WORD96 0x0002
280 #define GML_CLOCK_DETECT_BIT_WORD48 0x0004
281 #define GML_CLOCK_DETECT_BIT_SPDIF48 0x0008
282 #define GML_CLOCK_DETECT_BIT_SPDIF96 0x0010
285 #define GML_CLOCK_DETECT_BIT_ESYNC 0x0020
286 #define GML_CLOCK_DETECT_BIT_ADAT 0x0040
295 #define LAYLA20_CLOCK_INTERNAL 0
307 #define GD_CLOCK_NOCHANGE 0
311 #define GD_CLOCK_UNDEF 0xff
320 #define GD_SPDIF_STATUS_NOCHANGE 0
323 #define GD_SPDIF_STATUS_UNDEF 0xff
332 #define LAYLA20_OUTPUT_CLOCK_SUPER 0
342 #define GD24_96000 0x0
343 #define GD24_48000 0x1
344 #define GD24_44100 0x2
345 #define GD24_32000 0x3
346 #define GD24_22050 0x4
347 #define GD24_16000 0x5
348 #define GD24_11025 0x6
349 #define GD24_8000 0x7
350 #define GD24_88200 0x8
351 #define GD24_EXT_SYNC 0x9
360 #define ASIC_ALREADY_LOADED 0x1
361 #define ASIC_NOT_LOADED 0x0
387 * three bytes per sample; if you had two samples 0x112233 and 0x445566
419 #define DSP_AUDIOFORM_MS_8 0 /* 8 bit mono */
430 #define DSP_AUDIOFORM_INVALID 0xFF /* Invalid audio format */
443 * the interleave factor. So, 32 bit interleave by 6 is 0x86 and
444 * 16 bit interleave by 16 is (0x40 | 0x10) = 0x50.
448 #define DSP_AUDIOFORM_SUPER_INTERLEAVE_16LE 0x40
449 #define DSP_AUDIOFORM_SUPER_INTERLEAVE_24LE 0xc0
450 #define DSP_AUDIOFORM_SUPER_INTERLEAVE_32LE 0x80
459 #define GML_CONVERTER_ENABLE 0x0010
460 #define GML_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1,
461 consumer == 0 */
462 #define GML_SPDIF_SAMPLE_RATE0 0x0040
463 #define GML_SPDIF_SAMPLE_RATE1 0x0080
464 #define GML_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels,
465 0 == one channel */
466 #define GML_SPDIF_NOT_AUDIO 0x0200
467 #define GML_SPDIF_COPY_PERMIT 0x0400
468 #define GML_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */
469 #define GML_ADAT_MODE 0x1000 /* 1 == ADAT mode, 0 == S/PDIF mode */
470 #define GML_SPDIF_OPTICAL_MODE 0x2000 /* 1 == optical mode, 0 == RCA mode */
471 #define GML_SPDIF_CDROM_MODE 0x3000 /* 1 == CDROM mode,
472 * 0 == RCA or optical mode */
473 #define GML_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed,
474 0 == single speed */
476 #define GML_DIGITAL_IN_AUTO_MUTE 0x800000
478 #define GML_96KHZ (0x0 | GML_DOUBLE_SPEED_MODE)
479 #define GML_88KHZ (0x1 | GML_DOUBLE_SPEED_MODE)
480 #define GML_48KHZ 0x2
481 #define GML_44KHZ 0x3
482 #define GML_32KHZ 0x4
483 #define GML_22KHZ 0x5
484 #define GML_16KHZ 0x6
485 #define GML_11KHZ 0x7
486 #define GML_8KHZ 0x8
487 #define GML_SPDIF_CLOCK 0x9
488 #define GML_ADAT_CLOCK 0xA
489 #define GML_WORD_CLOCK 0xB
490 #define GML_ESYNC_CLOCK 0xC
491 #define GML_ESYNCx2_CLOCK 0xD
493 #define GML_CLOCK_CLEAR_MASK 0xffffbff0
495 #define GML_DIGITAL_MODE_CLEAR_MASK 0xffffcfff
496 #define GML_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f
505 #define MIA_32000 0x0040
506 #define MIA_44100 0x0042
507 #define MIA_48000 0x0041
508 #define MIA_88200 0x0142
509 #define MIA_96000 0x0141
511 #define MIA_SPDIF 0x00000044
512 #define MIA_SPDIF96 0x00000144
523 #define E3G_CONVERTER_ENABLE 0x0010
524 #define E3G_SPDIF_PRO_MODE 0x0020 /* Professional S/PDIF == 1,
525 consumer == 0 */
526 #define E3G_SPDIF_SAMPLE_RATE0 0x0040
527 #define E3G_SPDIF_SAMPLE_RATE1 0x0080
528 #define E3G_SPDIF_TWO_CHANNEL 0x0100 /* 1 == two channels,
529 0 == one channel */
530 #define E3G_SPDIF_NOT_AUDIO 0x0200
531 #define E3G_SPDIF_COPY_PERMIT 0x0400
532 #define E3G_SPDIF_24_BIT 0x0800 /* 1 == 24 bit, 0 == 20 bit */
533 #define E3G_DOUBLE_SPEED_MODE 0x4000 /* 1 == double speed,
534 0 == single speed */
535 #define E3G_PHANTOM_POWER 0x8000 /* 1 == phantom power on,
536 0 == phantom power off */
538 #define E3G_96KHZ (0x0 | E3G_DOUBLE_SPEED_MODE)
539 #define E3G_88KHZ (0x1 | E3G_DOUBLE_SPEED_MODE)
540 #define E3G_48KHZ 0x2
541 #define E3G_44KHZ 0x3
542 #define E3G_32KHZ 0x4
543 #define E3G_22KHZ 0x5
544 #define E3G_16KHZ 0x6
545 #define E3G_11KHZ 0x7
546 #define E3G_8KHZ 0x8
547 #define E3G_SPDIF_CLOCK 0x9
548 #define E3G_ADAT_CLOCK 0xA
549 #define E3G_WORD_CLOCK 0xB
550 #define E3G_CONTINUOUS_CLOCK 0xE
552 #define E3G_ADAT_MODE 0x1000
553 #define E3G_SPDIF_OPTICAL_MODE 0x2000
555 #define E3G_CLOCK_CLEAR_MASK 0xbfffbff0
556 #define E3G_DIGITAL_MODE_CLEAR_MASK 0xffffcfff
557 #define E3G_SPDIF_FORMAT_CLEAR_MASK 0xfffff01f
560 #define E3G_CLOCK_DETECT_BIT_WORD96 0x0001
561 #define E3G_CLOCK_DETECT_BIT_WORD48 0x0002
562 #define E3G_CLOCK_DETECT_BIT_SPDIF48 0x0004
563 #define E3G_CLOCK_DETECT_BIT_ADAT 0x0004
564 #define E3G_CLOCK_DETECT_BIT_SPDIF96 0x0008
571 #define E3G_FREQ_REG_MAX 0xffff
574 #define E3G_GINA3G_BOX_TYPE 0x00
575 #define E3G_LAYLA3G_BOX_TYPE 0x10
576 #define E3G_ASIC_NOT_LOADED 0xffff
577 #define E3G_BOX_TYPE_MASK 0xf0
580 #define INDIGO_EXPRESS_32000 0x02
581 #define INDIGO_EXPRESS_44100 0x01
582 #define INDIGO_EXPRESS_48000 0x00
583 #define INDIGO_EXPRESS_DOUBLE_SPEED 0x10
584 #define INDIGO_EXPRESS_QUAD_SPEED 0x04
585 #define INDIGO_EXPRESS_CLOCK_MASK 0x17
591 * this is the magic number for the hardware that gives you 0 dB at -10.
595 #define GL20_INPUT_GAIN_MAGIC_NUMBER 0xC8
615 #define MONITOR_ARRAY_SIZE 0x180
616 #define VMIXER_ARRAY_SIZE 0x40
646 __le32 comm_size; /* size of this object 0x000 4 */
647 __le32 flags; /* See Appendix A below 0x004 4 */
648 __le32 unused; /* Unused entry 0x008 4 */
649 __le32 sample_rate; /* Card sample rate in Hz 0x00c 4 */
650 __le32 handshake; /* DSP command handshake 0x010 4 */
651 __le32 cmd_start; /* Chs. to start mask 0x014 4 */
652 __le32 cmd_stop; /* Chs. to stop mask 0x018 4 */
653 __le32 cmd_reset; /* Chs. to reset mask 0x01c 4 */
654 __le16 audio_format[DSP_MAXPIPES]; /* Chs. audio format 0x020 32*2 */
656 /* Chs. Physical sglist addrs 0x060 32*8 */
658 /* Positions for ea. ch. 0x160 32*4 */
660 /* VU meters 0x1e0 32*1 */
662 /* Peak meters 0x200 32*1 */
664 /* Output gain 0x220 16*1 */
666 /* Input gain 0x230 16*1 */
668 /* Monitor map 0x240 0x180 */
670 /* Gina/Darla play filters - obsolete 0x3c0 168*4 */
672 /* Gina/Darla record filters - obsolete 0x660 192*4 */
674 /* MIDI input data transfer buffer 0x960 256*2 */
675 u8 gd_clock_state; /* Chg Gina/Darla clock state 0xb60 1 */
676 u8 gd_spdif_status; /* Chg. Gina/Darla S/PDIF state 0xb61 1 */
677 u8 gd_resampler_state; /* Should always be 3 0xb62 1 */
678 u8 filler2; /* 0xb63 1 */
679 __le32 nominal_level_mask; /* -10 level enable mask 0xb64 4 */
680 __le16 input_clock; /* Chg. Input clock state 0xb68 2 */
681 __le16 output_clock; /* Chg. Output clock state 0xb6a 2 */
682 __le32 status_clocks; /* Current Input clock state 0xb6c 4 */
683 __le32 ext_box_status; /* External box status 0xb70 4 */
684 __le32 cmd_add_buffer; /* Pipes to add (obsolete) 0xb74 4 */
686 /* # of bytes free in MIDI output FIFO 0xb78 4 */
687 __le32 unused2; /* Cyclic pipes 0xb7c 4 */
689 /* Mona, Gina24, Layla24, 3G ctrl reg 0xb80 4 */
690 __le32 e3g_frq_register; /* 3G frequency register 0xb84 4 */
691 u8 filler[24]; /* filler 0xb88 24*1 */
693 /* Vmixer levels 0xba0 64*1 */
695 /* MIDI output data 0xbe0 32*1 */