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17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
72 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
78 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
80 /* 8 bpp Red */
81 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
84 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
87 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
88 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
94 /* 8 bpp RGB */
95 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
96 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
99 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian…
100 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian…
101 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian…
102 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian…
104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
109 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian…
110 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian…
111 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian…
112 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian…
114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
119 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
120 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
149 * IEEE 754-2008 binary16 half-precision float
150 * [15:0] sign:exponent:mantissa 1:5:10
159 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little end…
160 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little end…
161 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little end…
162 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little end…
164 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
165 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endi…
166 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
167 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. N…
171 * 16-xx padding occupy lsb
173 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:…
174 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:…
175 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16…
179 * 16-xx padding occupy lsb except Y410
181 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
182 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
183 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
185 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 littl…
186 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4…
187 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 lit…
193 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
195 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
198 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
200 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
204 * 1-plane YUV 4:2:0
206 * then V), but the exact Linear layout is undefined.
207 * These formats can only be used with a non-Linear modifier.
209 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
210 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
215 * index 1 = A plane, [7:0] A
217 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
218 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
219 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
220 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
221 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
222 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
223 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
224 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
229 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
231 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
233 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
234 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
235 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
236 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
237 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
238 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
242 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
244 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
249 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
251 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per …
256 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
258 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
263 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
265 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per …
270 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
272 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per …
274 /* 3 plane non-subsampled (444) YCbCr
277 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
280 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
282 /* 3 plane non-subsampled (444) YCrCb
285 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
288 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
293 * index 1: Cb plane, [7:0] Cb
296 * index 1: Cr plane, [7:0] Cr
299 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) plane…
300 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) plane…
301 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) plane…
302 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) plane…
303 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) plane…
304 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) plane…
305 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) plane…
306 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) plane…
307 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
308 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
314 * Format modifiers describe, typically, a re-ordering or modification
318 * The upper 8 bits of the format modifier are a vendor-id as assigned
338 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
352 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
354 * compatibility, in cases where a vendor-specific definition already exists and
359 * generic layouts (such as pixel re-ordering), which may have
360 * independently-developed support across multiple vendors.
363 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
388 * Just plain linear layout. Note that this is different from no specifying any
390 * which tells the driver to also take driver-internal information into account
398 * Intel X-tiling layout
401 * in row-major layout. Within the tile bytes are laid out row-major, with
402 * a platform-dependent stride. On top of that the memory can apply
403 * platform-depending swizzling of some higher address bits into bit6.
405 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
407 * cross-driver sharing. It exists since on a given platform it does uniquely
408 * identify the layout in a simple way for i915-specific userspace, which
412 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
415 * Intel Y-tiling layout
418 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
419 * chunks column-major, with a platform-dependent height. On top of that the
420 * memory can apply platform-depending swizzling of some higher address bits
423 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
425 * cross-driver sharing. It exists since on a given platform it does uniquely
426 * identify the layout in a simple way for i915-specific userspace, which
433 * Intel Yf-tiling layout
435 * This is a tiled layout using 4Kb tiles in row-major layout.
436 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
437 * are arranged in four groups (two wide, two high) with column-major layout.
439 * out as 2x2 column-major.
441 * either a square block or a 2:1 unit.
450 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
451 * The main surface will be plane index 0 and must be Y/Yf-tiled,
452 * the CCS will be plane index 1.
460 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
468 * Intel color control surfaces (CCS) for Gen-12 render compression.
470 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
471 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
474 * Y-tile widths.
479 * Intel color control surfaces (CCS) for Gen-12 media compression
481 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
482 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
485 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
486 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
492 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
494 * Macroblocks are laid in a Z-shape, and each pixel data is following the
497 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
499 * - multiple of 128 pixels for the width
500 * - multiple of 32 pixels for the height
502 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
504 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
507 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
509 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
519 * Implementation may be platform and base-format specific.
526 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
533 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
536 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
539 * Vivante 64x64 super-tiling layout
541 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
542 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
546 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
551 * Vivante 4x4 tiling layout for dual-pipe
555 * compared to the non-split tiled layout.
560 * Vivante 64x64 super-tiling layout for dual-pipe
562 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
564 * therefore halved compared to the non-split super-tiled layout.
575 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
592 * ---- ----- -----------------------------------------------------------------
596 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
598 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
600 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
602 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
605 * Note there is no log2(width) parameter. Some portions of the
607 * to use due to lack of support elsewhere, and has no known
610 * 11:9 - Reserved (To support 2D-array textures with variable array stride
631 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
632 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
633 * 2 = Gob Height 8, Turing+ Page Kind mapping
642 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
643 * 1 = Desktop GPU and Tegra Xavier+ Layout
648 * 1 = ROP/3D, layout 1, exact compression format implied by Page
658 * 55:25 - Reserved for future use. Must be zero.
670 * with block-linear layouts, is remapped within drivers to the value 0xfe,
671 * which corresponds to the "generic" kind used for simple single-sample
672 * uncompressed color formats on Fermi - Volta GPUs.
687 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
689 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
691 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
695 * 1 == TWO_GOBS
704 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \ argument
705 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
710 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
723 * type, and the next 24 bits for parameters. Top 8 bits are the
726 #define __fourcc_mod_broadcom_param_shift 8
732 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
734 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
743 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
746 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
749 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
753 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
754 * tiles) or right-to-left (odd rows of 4k tiles).
756 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
777 * and UV. Some SAND-using hardware stores UV in a separate tiled
782 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \ argument
783 fourcc_mod_broadcom_code(2, v)
784 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \ argument
785 fourcc_mod_broadcom_code(3, v)
786 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \ argument
787 fourcc_mod_broadcom_code(4, v)
788 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \ argument
789 fourcc_mod_broadcom_code(5, v)
817 * the assumption is that a no-XOR tiling modifier will be created.
825 * It provides fine-grained random access and minimizes the amount of data
830 * and different devices or use-cases may support different combinations.
862 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
865 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
876 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
879 * AFBC block-split
885 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
897 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
900 * AFBC copy-block restrict
902 * Buffers with this flag must obey the copy-block restriction. The restriction
903 * is such that there are no copy-blocks referring across the border of 8x8
904 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
906 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
911 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
912 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
918 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
923 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
926 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
929 * AFBC double-buffer
931 * Indicates that the buffer is allocated in a layout safe for front-buffer
934 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
939 * Indicates that the buffer includes per-superblock content hints.
941 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
953 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
956 * Arm 16x16 Block U-Interleaved modifier
963 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
975 * both in row-major order.
977 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
989 * The underlying storage is considered to be 3 components, 8bit or 10-bit
991 * - DRM_FORMAT_YUV420_8BIT
992 * - DRM_FORMAT_YUV420_10BIT
994 * The first 8 bits of the mode defines the layout, then the following 8 bits
1001 #define __fourcc_mod_amlogic_options_shift 8
1016 * - a body content organized in 64x32 superblocks with 4096 bytes per
1018 * - a 32 bytes per 128x64 header block
1022 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1036 * be accessible by the user-space clients, but only accessible by the
1039 * The user-space clients should expect a failure while trying to mmap
1040 * the DMA-BUF handle returned by the producer.
1050 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1057 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)