Lines Matching defs:drm_amdgpu_info_device
950 struct drm_amdgpu_info_device { struct
952 __u32 device_id;
954 __u32 chip_rev;
955 __u32 external_rev;
957 __u32 pci_rev;
958 __u32 family;
959 __u32 num_shader_engines;
960 __u32 num_shader_arrays_per_engine;
962 __u32 gpu_counter_freq;
963 __u64 max_engine_clock;
964 __u64 max_memory_clock;
966 __u32 cu_active_number;
968 __u32 cu_ao_mask;
969 __u32 cu_bitmap[4][4];
971 __u32 enabled_rb_pipes_mask;
972 __u32 num_rb_pipes;
973 __u32 num_hw_gfx_contexts;
974 __u32 _pad;
975 __u64 ids_flags;
977 __u64 virtual_address_offset;
979 __u64 virtual_address_max;
981 __u32 virtual_address_alignment;
983 __u32 pte_fragment_size;
984 __u32 gart_page_size;
986 __u32 ce_ram_size;
988 __u32 vram_type;
990 __u32 vram_bit_width;
992 __u32 vce_harvest_config;
994 __u32 gc_double_offchip_lds_buf;
996 __u64 prim_buf_gpu_addr;
998 __u64 pos_buf_gpu_addr;
1000 __u64 cntl_sb_buf_gpu_addr;
1002 __u64 param_buf_gpu_addr;
1003 __u32 prim_buf_size;
1004 __u32 pos_buf_size;
1005 __u32 cntl_sb_buf_size;
1006 __u32 param_buf_size;
1008 __u32 wave_front_size;
1010 __u32 num_shader_visible_vgprs;
1012 __u32 num_cu_per_sh;
1014 __u32 num_tcc_blocks;
1016 __u32 gs_vgt_table_depth;
1018 __u32 gs_prim_buffer_depth;
1020 __u32 max_gs_waves_per_vgt;
1021 __u32 _pad1;
1023 __u32 cu_ao_bitmap[4][4];
1025 __u64 high_va_offset;
1027 __u64 high_va_max;
1029 __u32 pa_sc_tile_steering_override;
1031 __u64 tcc_disabled_mask;