sound/sof/dai-intel.h

1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
52 /* DMIC max. four controllers for eight microphone channels */
55 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
61 	uint32_t mclk_rate;	/* mclk frequency in Hz */
62 	uint32_t fsync_rate;	/* fsync frequency in Hz */
63 	uint32_t bclk_rate;	/* bclk frequency in Hz */
87 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
91 	uint32_t rate;  member
95 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
99 	uint32_t rate;  member
106 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
149  * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
150  * multi-mode capable and there may be denied mic clock frequencies between
152  * avoid the driver to set clock to an illegal rate.
154  * The duty cycle could be set to 48-52% if not known. Generally these
158  * The microphone clock needs to be usually about 50-80 times the used audio
159  * sample rate. With highest sample rates above 48 kHz this can relaxed
174 	uint32_t pdmclk_min;	/**< Minimum microphone clock in Hz (100000..N) */
175 	uint32_t pdmclk_max;	/**< Maximum microphone clock in Hz (min...N) */
177 	uint32_t fifo_fs;	/**< FIFO sample rate in Hz (8000..96000) */
183 	uint16_t duty_max;	/**< Max. mic clock duty cycle in % (min..80) */
189 	uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */