Lines Matching +full:half +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
26 u16 tg_width; /* Type-group width (in bits) */
48 /* VCAP Type-Group values */
51 #define VCAP_TG_HALF 2 /* Half entry */
57 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
58 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
59 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
63 #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
64 #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
65 #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
81 #define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
83 #define TCAM_BIST_CTRL_TCAM_BIST BIT(1)
84 #define TCAM_BIST_CTRL_TCAM_INIT BIT(0)
86 #define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8)
87 #define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7)
88 #define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6)
92 #define TCAM_BIST_STAT_BIST_RT_ERR BIT(15)
93 #define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14)
94 #define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13)
95 #define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12)
96 #define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11)
97 #define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10)
98 #define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9)
99 #define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8)
100 #define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7)
101 #define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6)
102 #define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5)
103 #define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4)
104 #define TCAM_BIST_STAT_BIST_RUN BIT(3)
105 #define TCAM_BIST_STAT_BIST_ERR BIT(2)
106 #define TCAM_BIST_STAT_BIST_BUSY BIT(1)
107 #define TCAM_BIST_STAT_TCAM_RDY BIT(0)
114 /* IS2 half key types */
126 /* IS2 half key type mask for matching any IP */
150 #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
154 /* IS2 quarter key - SMAC_SIP4 */
275 /* IS1 half key types */
304 /* Specific Fields for IS1 Half Key S1_NORMAL */
319 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */