Lines Matching full:transmit
64 #define SSCR0_TUM BIT(23) /* Transmit FIFO underrun interrupt mask */
72 #define SSCR1_TIE BIT(1) /* Transmit FIFO Interrupt Enable */
76 #define SSCR1_MWDS BIT(5) /* Microwire Transmit Data Size */
79 #define SSSR_TNF BIT(2) /* Transmit FIFO Not Full */
82 #define SSSR_TFS BIT(5) /* Transmit FIFO Service Request */
89 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
92 #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
100 #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
103 #define CE4100_SSCR1_TFT GENMASK(7, 6) /* Transmit FIFO Threshold (mask) */
117 #define QUARK_X1000_SSSR_TFL_MASK GENMASK(12, 8) /* Transmit FIFO Level mask */
120 #define QUARK_X1000_SSCR1_TFT GENMASK(10, 6) /* Transmit FIFO Threshold (mask) */
137 #define SSCR1_TSRE BIT(21) /* Transmit Service Request Enable */
139 #define SSCR1_RWOT BIT(23) /* Receive Without Transmit */
152 #define SSSR_TUR BIT(21) /* Transmit FIFO Under Run */